scholarly journals A 1 V 92 dB SNDR 10 kHz Bandwidth Second-Order Asynchronous Delta-Sigma Modulator for Biomedical Signal Processing

Sensors ◽  
2020 ◽  
Vol 20 (15) ◽  
pp. 4137
Author(s):  
Vilém Kledrowetz ◽  
Lukáš Fujcik ◽  
Roman Prokop ◽  
Jiří Háze

In this paper, a second-order asynchronous delta-sigma modulator (ADSM) is proposed based on the active-RCintegrators. The ADSM is implemented in the 0.18 μ m CMOS Logic or Mixed-Signal/RF, General Purpose process from the Taiwan Semiconductor Manufacturing Company with a center frequency of 848 kHz at a supply voltage of 1 V with a 92 dB peak signal-to-noise and distortion ratio ( S N D R ), which corresponds to 15 bit resolution. These parameters were achieved in all the endogenous bioelectric signals bandwidth of 10 kHz. The ADSM dissipated 295 μ W and had an area of 0.54 mm 2 . The proposed ADSM with a high resolution, wide bandwidth, and rail-to-rail input voltage range provides the universal solution for endogenous bioelectric signal processing.

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6456
Author(s):  
Fernando Cardes ◽  
Nikhita Baladari ◽  
Jihyun Lee ◽  
Andreas Hierlemann

This article reports on a compact and low-power CMOS readout circuit for bioelectrical signals based on a second-order delta-sigma modulator. The converter uses a voltage-controlled, oscillator-based quantizer, achieving second-order noise shaping with a single opamp-less integrator and minimal analog circuitry. A prototype has been implemented using 0.18 μm CMOS technology and includes two different variants of the same modulator topology. The main modulator has been optimized for low-noise, neural-action-potential detection in the 300 Hz–6 kHz band, with an input-referred noise of 5.0 μVrms, and occupies an area of 0.0045 mm2. An alternative configuration features a larger input stage to reduce low-frequency noise, achieving 8.7 μVrms in the 1 Hz–10 kHz band, and occupies an area of 0.006 mm2. The modulator is powered at 1.8 V with an estimated power consumption of 3.5 μW.


2020 ◽  
Vol 15 (3) ◽  
pp. 1-12
Author(s):  
Ana Isabela Araújo Cunha ◽  
Antonio José Sobrinho De Sousa ◽  
Edson Pinto Santana ◽  
Robson Nunes De Lima ◽  
Fabian Souza De Andrade ◽  
...  

This work presents a CMOS four quadrant analog multiplier architecture for application as the synapse element in analog cellular neural networks. For this reason, the circuit has voltage-mode inputs and a current-mode output and the chief design targets are compactness and low energy consumption. A signal application method is proposed that avoids voltage reference generators, which contributes to reduce sensitivity to supply voltage variation. Performance analysis through simulation has been accomplished for a design in CMOS 130 nm technology with 163 µm2 total active area. The circuit features ±50 mV input voltage range, 86 µW static power and ‑28.4 dB maximum total harmonic distortion. A simple technique for manual calibration is also presented.


Author(s):  
Astria Nur Irfansyah ◽  
Long Pham ◽  
Andrew Nicholson ◽  
Torsten Lehmann ◽  
Julian Jenkins ◽  
...  

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