scholarly journals An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction

Sensors ◽  
2020 ◽  
Vol 20 (8) ◽  
pp. 2172 ◽  
Author(s):  
Zhipeng Song ◽  
Zhixiang Zhao ◽  
Hongsen Yu ◽  
Jingwu Yang ◽  
Xi Zhang ◽  
...  

This paper presented a non-uniform multiphase (NUMP) time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) with real-time automatic temperature compensation. NUMP-TDC is a novel, low-cost, high-performance TDC that has achieved an excellent performance in Altera Cyclone V FPGA. The root mean square (RMS) for the intrinsic timing resolution was 2.3 ps. However, the propagation delays in the delay chain of some FPGAs (for example, the Altera Cyclone 10 LP) vary significantly as the temperature changes. Thus, the timing performances of NUMP-TDCs implemented in those FPGAs are significantly impacted by temperature fluctuations. In this study, a simple method was developed to monitor variations in propagation delays using two registers deployed at both ends of the delay chain and compensate for changes in propagation delay using a look-up table (LUT). When the variations exceeded a certain threshold, the LUT for the delay correction was updated, and a bin-by-bin correction was launched. Using this correction approach, a resolution of 8.8 ps RMS over a wide temperature range (5 °C to 80 °C) had been achieved in a NUMP-TDC implemented in a Cyclone 10 LP FPGA.

1978 ◽  
Vol 150 (3) ◽  
pp. 575-580 ◽  
Author(s):  
G. Lenzi ◽  
P. Podini ◽  
R. Reverberi ◽  
K. Pernestål

Author(s):  
Cindy X. Jiang ◽  
Tom T. Hartley ◽  
Joan E. Carletta

Hardware implementation of fractional-order differentiators and integrators requires careful consideration of issues of system quality, hardware cost, and speed. This paper proposes using field programmable gate arrays (FPGAs) to implement fractional-order systems, and demonstrates the advantages that FPGAs provide. As an illustration, the fundamental operators to a real power is approximated via the binomial expansion of the backward difference. The resulting high-order FIR filter is implemented in a pipelined multiplierless architecture on a low-cost Spartan-3 FPGA. Unlike common digital implementations in which all filter coefficients have the same word length, this approach exploits variable word length for each coefficient. Our system requires twenty percent less hardware than a system of comparable quality generated by Xilinx’s System Generator on its most area-efficient multiplierless setting. The work shows an effective way to implement a high quality, high throughput approximation to a fractional-order system, while maintaining less cost than traditional FPGA-based designs.


Nanomaterials ◽  
2021 ◽  
Vol 11 (10) ◽  
pp. 2636
Author(s):  
Fenghui Cao ◽  
Jia Xu ◽  
Xinci Zhang ◽  
Bei Li ◽  
Xiao Zhang ◽  
...  

We developed a simple method to fabricate SiO2-sphere-supported N-doped CNTs (NCNTs) for electromagnetic wave (EMW) absorption. EMW absorption was tuned by adsorption of the organic agent on the precursor of the catalysts. The experimental results show that the conductivity loss and polarization loss of the sample are improved. Meanwhile, the impedance matching characteristics can also be adjusted. When the matching thickness was only 1.5 mm, the optimal 3D structure shows excellent EMW absorption performance, which is better than most magnetic carbon matrix composites. Our current approach opens up an effective way to develop low-cost, high-performance EMW absorbers.


2021 ◽  
Author(s):  
Nicholas Parkyn

Emerging heterogeneous computing, computing at the edge, machine learning and AI at the edge technology drives approaches and techniques for processing and analysing onboard instrument data in near real-time. The author has used edge computing and neural networks combined with high performance heterogeneous computing platforms to accelerate AI workloads. Heterogeneous computing hardware used is readily available, low cost, delivers impressive AI performance and can run multiple neural networks in parallel. Collecting, processing and machine learning from onboard instruments data in near real-time is not a trivial problem due to data volumes, complexities of data filtering, data storage and continual learning. Little research has been done on continual machine learning which aims at a higher level of machine intelligence through providing the artificial agents with the ability to learn from a non-stationary and never-ending stream of data. The author has applied the concept of continual learning to building a system that continually learns from actual boat performance and refines predictions previously done using static VPP data. The neural networks used are initially trained using the output from traditional VPP software and continue to learn from actual data collected under real sailing conditions. The author will present the system design, AI, and edge computing techniques used and the approaches he has researched for incremental training to realise continual learning.


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