10 ps resolution, 160 ns full scale range and less than 1.5% differential non-linearity time-to-digital converter module for high performance timing measurements

2012 ◽  
Vol 83 (7) ◽  
pp. 074703 ◽  
Author(s):  
B. Markovic ◽  
D. Tamborini ◽  
F. Villa ◽  
S. Tisa ◽  
A. Tosi ◽  
...  
Keyword(s):  
High Performance ◽  
Full Scale ◽  
Digital Converter ◽  
Time To Digital Converter ◽  
Scale Range ◽  
Performance Timing

scholarly journals Multichannel low power time-to-digital converter card with 21 ps precision and full scale range up to 10 μs

2014 ◽  
Vol 85 (11) ◽  
pp. 114703 ◽  
Author(s):  
D. Tamborini ◽  
D. Portaluppi ◽  
F. Villa ◽  
S. Tisa ◽  
A. Tosi
Keyword(s):  
Low Power ◽  
Full Scale ◽  
Digital Converter ◽  
Time To Digital Converter ◽  
Scale Range

scholarly journals Dual channel time‐to‐digital converter module with 10 ps resolution and 320 ns full scale range

2015 ◽  
Vol 51 (13) ◽  
pp. 994-996 ◽  
Author(s):  
D. Tamborini ◽  
D. Portaluppi ◽  
F. Villa ◽  
F. Zappa
Keyword(s):  
Full Scale ◽  
Digital Converter ◽  
Time To Digital Converter ◽  
Dual Channel ◽  
Scale Range

scholarly journals An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction

Sensors ◽  
2020 ◽  
Vol 20 (8) ◽  
pp. 2172 ◽  
Author(s):  
Zhipeng Song ◽  
Zhixiang Zhao ◽  
Hongsen Yu ◽  
Jingwu Yang ◽  
Xi Zhang ◽  
...  
Keyword(s):  
Real Time ◽  
High Performance ◽  
Low Cost ◽  
Propagation Delay ◽  
Temperature Correction ◽  
Digital Converter ◽  
Simple Method ◽  
Time To Digital Converter ◽  
Propagation Delays ◽  
Field Programmable

This paper presented a non-uniform multiphase (NUMP) time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) with real-time automatic temperature compensation. NUMP-TDC is a novel, low-cost, high-performance TDC that has achieved an excellent performance in Altera Cyclone V FPGA. The root mean square (RMS) for the intrinsic timing resolution was 2.3 ps. However, the propagation delays in the delay chain of some FPGAs (for example, the Altera Cyclone 10 LP) vary significantly as the temperature changes. Thus, the timing performances of NUMP-TDCs implemented in those FPGAs are significantly impacted by temperature fluctuations. In this study, a simple method was developed to monitor variations in propagation delays using two registers deployed at both ends of the delay chain and compensate for changes in propagation delay using a look-up table (LUT). When the variations exceeded a certain threshold, the LUT for the delay correction was updated, and a bin-by-bin correction was launched. Using this correction approach, a resolution of 8.8 ps RMS over a wide temperature range (5 °C to 80 °C) had been achieved in a NUMP-TDC implemented in a Cyclone 10 LP FPGA.

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