scholarly journals Fully Differential Touch Screen Controller with Wide Input Dynamic Range for Thin Displays

Sensors ◽  
2020 ◽  
Vol 20 (3) ◽  
pp. 837
Author(s):  
Chang-Ju Lee ◽  
Jong Kang Park ◽  
Han-Eol Seo ◽  
Junho Huh ◽  
Jung-Hoon Chun
Keyword(s):  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
Touch Screen ◽  
Cmos Process ◽  
Charge Amplifier ◽  
Test Chip ◽  
Maximum Peak ◽  
Fully Differential ◽  
Coupling Capacitance ◽  
The Time Domain

As today’s smartphone displays become thinner, the coupling capacitance between the display electrodes and touch screen panel (TSP) electrodes is increasing significantly. The increased capacitance easily introduces time-varying display signals into the TSP, deteriorating the touch performance. In this research, we demonstrate that the maximum peak display noise in the time domain is approximately 30% of the maximum voltage difference of the display grayscale through analysis of the structure and operation of displays. Then, to mitigate display noise, we propose a circuit solution that uses a fully differential charge amplifier with an input dynamic range wider than the maximum peak of the display noise. A test chip was fabricated using a 0.35 μm CMOS process and achieved a signal-to-noise ratio of 41 dB for a 6-mm-diameter metal pillar touch when display pulses with 5-V swing were driven at 100 kHz.

Design of High Performance Sample Hold Amplifier for Pipeline ADC

2015 ◽  
Vol 743 ◽  
pp. 244-247
Author(s):  
R. Zou
Keyword(s):  
High Performance ◽  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
Sampling Rate ◽  
Cmos Process ◽  
Pipeline Adc ◽  
Analog To Digital ◽  
Fully Differential ◽  
Dc Gain ◽  
Spurious Free Dynamic Range

A fully-differential switched-capacitor sample-and-hold amplifier (SHA) used in a 10-bit 30-MS/s pipeline analog-to-digital converter (ADC) was designed using a 0.13-μm CMOS process. Flip-around architecture was used in the SHA circuit to lower the power consumption. A gain-boosted operational amplifier (OPAMP) was designed with a DC gain of 87 dB and a unit gain bandwidth of 388MHz at a phase margin of 75 degree. The simulated results have shown that the SHA circuit reaches a spurious free dynamic range (SFDR) of 94 dB and a signal-to-noise ratio (SNR) of 76 dB for a 10.18 MHz input signal with 30 MS/s sampling rate.

scholarly journals Mutual Capacitive Sensing Touch Screen Controller for Ultrathin Display with Extended Signal Passband Using Negative Capacitance

Sensors ◽  
2018 ◽  
Vol 18 (11) ◽  
pp. 3637 ◽  
Author(s):  
Chang-Ju Lee ◽  
Jong Park ◽  
Canxing Piao ◽  
Han-Eol Seo ◽  
Jaehyuk Choi ◽  
...  
Keyword(s):  
Signal To Noise Ratio ◽  
Phase Fluctuation ◽  
Touch Screen ◽  
Smart Devices ◽  
Cmos Process ◽  
Negative Capacitance ◽  
Driving Frequency ◽  
Large Coupling ◽  
Quadrature Demodulation ◽  
Coupling Capacitance

Flexible and thin displays for smart devices have a large coupling capacitance between the sensor electrode of the touch screen panel (TSP) and the display electrode. This increased coupling capacitance limits the signal passband to less than 100 kHz, resulting in a significant reduction in the received signal, with a driving frequency of several hundred kilohertz used for noise avoidance. To overcome this problem, we reduced the effective capacitance at the analog front-end by connecting a circuit with a negative capacitance in parallel with the coupling capacitance of the TSP. In addition, the in-phase and quadrature demodulation scheme was used to address the phase fluctuation between the signal and the clock during demodulation. We fabricated a test chip using the 0.35 µm CMOS process and obtained a signal-to-noise ratio of 43.2 dB for a 6 mm diameter metal pillar touch input.

scholarly journals Current Input Pixel-Level ADC with High SNR and Wide Dynamic Range for a Microbolometer

Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2354
Author(s):  
Jeongho Lee ◽  
Ilku Nam ◽  
DooHyung Woo
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Signal To Noise Ratio ◽  
Integration Time ◽  
Cmos Process ◽  
Readout Circuit ◽  
Power Supply Voltage ◽  
Analog To Digital ◽  
Current Input ◽  
Cell Circuit

A readout circuit incorporating a pixel-level analog-to-digital converter (ADC) is studied for two-dimensional medium wavelength infrared microbolometer arrays. The signal-to-noise ratio (SNR) and charge handling capacity of the unit cell circuit are improved by using the current input pixel-level ADC. The charge handling capacity of the integrator is appropriately extended to maximize the integration time regardless of the magnitude of the input current and low power supply voltage. The readout circuit was fabricated using a 0.35-μm 2-poly 4-metal CMOS process for a 640 × 512 array with a pixel size of 40 μm × 40 μm. The peak SNR and dynamic range are 77.1 and 80.1 dB, respectively, with a power consumption of 0.62 μW per pixel.

scholarly journals A double-differential-input/differential-output fully complementary and self-biased asynchronous CMOS comparator

2014 ◽  
Vol 27 (4) ◽  
pp. 649-661 ◽  
Author(s):  
Vladimir Milovanovic ◽  
Horst Zimmermann
Keyword(s):  
Supply Voltage ◽  
Signal To Noise Ratio ◽  
Harmonic Distortion ◽  
Propagation Delay ◽  
Data Converters ◽  
Cmos Process ◽  
Voltage Reference ◽  
Process Technology ◽  
Fully Differential ◽  
Voltage Swing

A novel fully complementary and fully differential asynchronous CMOS comparator architecture, that consists of a two-stage preamplifier cascaded with a latch, achieves a sub-100 ps propagation delay for a 50mVpp and higher input signal amplitudes under 1.1V supply and 2.1mWpower consumption. The proposed voltage comparator topology features two differential pairs of inputs (four in total) thus increasing signal-to-noise ratio (SNR) and noise immunity through rejection of the coupled noise components, reduced evenorder harmonic distortion, and doubled output voltage swing. In addition to that, the comparator is truly self-biased via negative feedback loop thereby eliminating the need for a voltage reference and suppressing the influence of process, supply voltage and ambient temperature variations. The described analog comparator prototype occupies 0.001mm2 in a purely digital 40 nm LP (low power) CMOS process technology. All the above mentioned merits make it highly attractive for use as a building block in implementation of the leadingedge system-on-chip (SoC) data transceivers and data converters.

scholarly journals Design of Two-Stage Fully-Differential Operational Transconductance Amplifier Using a Standard 0.35µm CMOS Process

2019 ◽  
Vol 7 (1) ◽  
Author(s):  
Tanya Vanessa Abaya ◽  
Frederick Ray I. Gomez
Keyword(s):  
Dynamic Range ◽  
Oxide Semiconductor ◽  
Total Output ◽  
Common Source ◽  
Cmos Process ◽  
Main Stage ◽  
Operational Transconductance Amplifier ◽  
Two Stage ◽  
Fully Differential ◽  
Transconductance Amplifier

The paper presents a design of a two-stage fully-differential operational transconductance amplifier (OTA) for a 10-bit 40-Msamples/s Nyquist rate analog-to-digital converter (ADC) using  a standard 0.35µm complementary metal-oxide semiconductor (CMOS) process.  A telescopic cascode topology is implemented as main stage, with common source amplifiers as output stage for the differential outputs. The open loop amplifier achieved a gain of 108dB, while the closed loop gain is at 12dB with settling time of less than 11ns for an accuracy of 0.5%.  Total output noise achieved is 63.4uVrms.  Loop unity gain bandwidth is 205MHz with phase margin of 77.6°. The design has a dynamic range of 88.3dB, and power consumption of 26.6mW from a 3V supply.

Advantageous Apodization Functions for Magnitude-Mode Fourier Transform Spectroscopy

1987 ◽  
Vol 41 (1) ◽  
pp. 93-98 ◽  
Author(s):  
Judy P. Lee ◽  
Melvin B. Comisarow
Keyword(s):  
Fourier Transform ◽  
Time Domain ◽  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
Time Domain Signal ◽  
Time Domain Data ◽  
Window Functions ◽  
Fourier Transform Spectra ◽  
The Time Domain ◽  
Ratio Reduction

A systematic examination of the efficacy of window functions for reducing the spectral skirt of magnitude-mode Fourier transform spectra is reported. The efficacy is examined for the general case of a damped time-domain signal, with specific cases ranging from undamped to essentially completely damped signals. The choice of the optimal window is dependent upon the required dynamic range and the amount of damping in the time-domain data. For a dynamic range of less than 100:1 and moderate damping, the Hamming window is the window of choice. For larger dynamic ranges or greater damping, the 3-term Blackman-Harris window and the Kaiser-Bessel window are the windows of choice. The 3-term Blackman-Harris window is preferred for a dynamic range of 1,000:1 and the Kaiser-Bessel window is preferred for a dynamic range of 10,000:1. The sensitivity (signal-to-noise ratio) reduction for windows is reported for a damping range from zero to essentially complete damping. All windows examined have the same sensitivity reduction within 25%.

A 2nd Order Delta-Sigma ADC for Pressure Sensor Interface

2013 ◽  
Vol 475-476 ◽  
pp. 554-559
Author(s):  
Jong Do Lee ◽  
Jae Hyeon Shin ◽  
Young Min Park ◽  
Yong Sik Kwak ◽  
Gil Cho Ahn
Keyword(s):  
Pressure Sensor ◽  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
Second Order ◽  
Cmos Process ◽  
Signal To Noise ◽  
Sensor Interface ◽  
Interface Circuit ◽  
Piezoresistive Pressure Sensor ◽  
Delta Sigma

A second order delta-sigma analog-to-digital converter (ADC) including a bandgap reference, a bias circuit for sensor, and a digital filter for the interface of piezoresistive pressure sensor is presented. The proposed sensor interface circuit is designed to target a pressure range from 0 to 100 psi. The prototype sensor interface circuit is implemented in a 0.35 μm CMOS process. The single-loop, 1-bit, second-order delta-sigma ADC operates at OSR of 256 achieves 80.5 dB dynamic range (DR), 79.6 dB peak signal-to-noise ratio (SNR), and 74.4 dB peak signal-to-noise and distortion ratio (SNDR) over a signal bandwidth of 7.8 kHz with 3.3V supply while consuming 0.33mW including on-chip reference and bias current for sensor. (in Performance Summary: 0.95mW)

scholarly journals Time-Gated Single-Photon Detection in Time-Domain Diffuse Optics: A Review

2020 ◽  
Vol 10 (3) ◽  
pp. 1101 ◽  
Author(s):  
Alberto Dalla Mora ◽  
Laura Di Sieno ◽  
Rebecca Re ◽  
Antonio Pifferi ◽  
Davide Contini
Keyword(s):  
Time Domain ◽  
Dynamic Range ◽  
Single Photon ◽  
Signal To Noise Ratio ◽  
Single Photon Detection ◽  
Photon Detection ◽  
Ratio Measurement ◽  
Diffuse Optics ◽  
Detection Strategy ◽  
The Time Domain

This work reviews physical concepts, technologies and applications of time-domain diffuse optics based on time-gated single-photon detection. This particular photon detection strategy is of the utmost importance in the diffuse optics field as it unleashes the full power of the time-domain approach by maximizing performances in terms of contrast produced by a localized perturbation inside the scattering medium, signal-to-noise ratio, measurement time and dynamic range, penetration depth and spatial resolution. The review covers 15 years of theoretical studies, technological progresses, proof of concepts and design of laboratory systems based on time-gated single-photon detection with also few hints on other fields where the time-gated detection strategy produced and will produce further impact.

An Over 120dB Dynamic Range Linear Response Single Exposure CMOS Image Sensor with Two-stage Lateral Overflow Integration Trench Capacitors

2020 ◽  
Vol 2020 (7) ◽  
pp. 143-1-143-6 ◽  
Author(s):  
Yasuyuki Fujihara ◽  
Maasa Murata ◽  
Shota Nakayama ◽  
Rihito Kuroda ◽  
Shigetoshi Sugawa
Keyword(s):  
Linear Response ◽  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Signal To Noise ◽  
Single Exposure ◽  
Two Stage ◽  
Noise Ratio ◽  
Maximum Signal

This paper presents a prototype linear response single exposure CMOS image sensor with two-stage lateral overflow integration trench capacitors (LOFITreCs) exhibiting over 120dB dynamic range with 11.4Me- full well capacity (FWC) and maximum signal-to-noise ratio (SNR) of 70dB. The measured SNR at all switching points were over 35dB thanks to the proposed two-stage LOFITreCs.

A Fully Differential Variable Gain Amplifier for Portable Impedance Sensing Applications

2019 ◽  
Vol 7 ◽  
Author(s):  
Jorge Pérez Bailón ◽  
Jaime Ramírez-Angulo ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Active Area ◽  
Variable Gain Amplifier ◽  
Cmos Process ◽  
Current Steering ◽  
Impedance Sensing ◽  
Variable Gain ◽  
Fully Differential ◽  
Sensing Applications ◽  
Constant Bandwidth

This paper presents a Variable Gain Amplifier (VGA) designed in a 0.18 μm CMOS process to operate in an impedance sensing interface. Based on a transconductance-transimpedance (TC-TI) approach with intermediate analog-controlled current steering, it exhibits a gain ranging from 5 dB to 38 dB with a constant bandwidth around 318 kHz, a power consumption of 15.5 μW at a 1.8 V supply and an active area of 0.021 mm2.

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