scholarly journals The Implementation of a Low Power Environmental Monitoring and Soil Moisture Measurement System Based on UHF RFID

Sensors ◽  
2019 ◽  
Vol 19 (24) ◽  
pp. 5527 ◽  
Author(s):  
Žiga Korošak ◽  
Nejc Suhadolnik ◽  
Anton Pleteršek
Keyword(s):  
Low Power ◽  
Measurement System ◽  
Radio Frequency Identification ◽  
Supply Voltage ◽  
Measurement Properties ◽  
Capacitance Measurement ◽  
Uhf Rfid ◽  
Active System ◽  
Ultra Low Power ◽  
Moisture Sensor

A smart sensor label based on the integration of ultra high frequency (UHF) radio frequency identification (RFID) technology and sensors is presented. The label is composed of a semi-active system that measures temperature, light, relative humidity and gravimetric water content (GWC) in the soil. The deployed system provides a simple, cost effective solution to monitor and control the growing of plants in modern agriculture and is intended be a part of a smart wireless sensor network (WSN) for agricultural monitoring. This paper is focused on analysis and development of a moisture sensor to measure GWC. It is based on a capacitance measurement solution, the accuracy of which is enhanced using several sensor driving frequencies. Thanks to the cancellation of supply voltage variations, the modeling of the GWC sensor and readout circuit was correct. The results we measured were close to modeled values. The maximum measurement resolution of the capacitive moisture sensor was 0.07 pF. To get the GWC from measured capacitance, a scale was used to weigh the mass of water in the soil. The comparison between capacitance measurement and calculated soil GWC is presented. The RFID measurement system has energy harvesting capabilities and an ultra-low power microcontroller, which uses embedded software to control the measurement properties. The microcontroller has to choose the appropriate model depending on the measured amplitude and chosen frequency to calculate the actual voltage on the sensing capacitor.

scholarly journals A 920-MHz Dual-Mode Receiver with Energy Harvesting for UHF RFID Tag and IoT

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 1042
Author(s):  
Peiqing Han ◽  
Zhaofeng Zhang ◽  
Yajun Xia ◽  
Niansong Mei
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
Radio Frequency Identification ◽  
Supply Voltage ◽  
High Sensitivity ◽  
Cmos Process ◽  
Uhf Rfid ◽  
Dual Mode ◽  
Operating Modes ◽  
On Chip

A low-power dual-mode receiver is presented for ultra-high-frequency (UHF) radio frequency identification (RFID) systems. The reconfigurable architecture of the tag is proposed to be compatible with low-power and high-sensitivity operating modes. The read range of RFID system and the lifetime of the tag are increased by photovoltaic, thermoelectric and RF energy-harvesting topology. The receiver is implemented in a 0.18-μm standard CMOS process and occupies an active area of 0.65 mm × 0.7 mm. For low-power mode, the tag is powered by the rectifier and the sensitivity is −18 dBm. For high-sensitivity mode, the maximum PCE of the fully on-chip energy harvester is 46.5% with over 1-μW output power and the sensitivity is −40 dBm with 880 nW power consumption under the supply voltage of 0.8 V.

scholarly journals Quasi-Adiabatic SRAM Based Silicon Physical Unclonable Function

2020 ◽  
Vol 1 (5) ◽  
Author(s):  
Yasuhiro Takahashi ◽  
Hiroki Koyasu ◽  
S. Dinesh Kumar ◽  
Himanshu Thapliyal
Keyword(s):  
Low Power ◽  
Radio Frequency Identification ◽  
Supply Voltage ◽  
Electronic Devices ◽  
Random Access ◽  
Cmos Process ◽  
Physical Unclonable Function ◽  
Ultra Low Power ◽  
Measurement Results ◽  
Simulation Results

Abstract Silicon Physical Unclonable Function (PUF) is a general hardware security primitive for security vulnerabilities. Recently, Quasi-adiabatic logic based physical unclonable function (QUALPUF) has ultra low-power dissipation; hence it is suitable to implement in low-power portable electronic devices such radio frequency identification (RFID) and wireless sensor networks (WSN), etc. In this paper, we present a design of 4-bit QUALPUF which is based on static random access memory (SRAM) for low-power portable electronic devices and then shows the post-layout simulation and measurement results. To evaluate the uniqueness and reliability, the 4-bit QUALPUF is implemented in 0.18 $$\upmu$$ μ m standard CMOS process with 1.8 V supply voltage. The 4-bit QUALPUF occupies 58.7$$\times$$ × 15.7 $$\upmu \mathrm {m}^{2}$$ μ m 2 of layout area. The post-layout simulation results illustrate that the uniqueness calculated from the inter-die HDs of the 4-bit QUALPUF is 47.58%, the average reliability is 95.10%, and the the energy dissipation is 29.73 fJ/cycle/bit. The functional measurement results of the fabricated chip are the same as the post-layout simulation results.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

Ultra-low-power clock generation circuit for EPC standard UHF RFID transponders

2008 ◽  
Vol 44 (3) ◽  
pp. 199 ◽  
Author(s):  
F. Song ◽  
J. Yin ◽  
H.L. Liao ◽  
R. Huang
Keyword(s):  
Low Power ◽  
Uhf Rfid ◽  
Ultra Low Power ◽  
Clock Generation

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Circuit World ◽  
2020 ◽  
Vol 46 (3) ◽  
pp. 183-192
Author(s):  
Muhammad Yasir Faheem ◽  
Shun'an Zhong ◽  
Xinghua Wang ◽  
Muhammad Basit Azeem
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Supply Voltage ◽  
Main Idea ◽  
Cost Effective ◽  
Cmos Technology ◽  
Sar Adc ◽  
Ultra Low Power ◽  
Content Type ◽  
Analogue To Digital

Purpose Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC. Design/methodology/approach A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration. Findings The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms. Originality/value The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

scholarly journals Ultra low power mixer with out-of-band RF energy harvesting for wireless sensor networks applications

2020 ◽  
Vol 40 (1) ◽  
pp. 1-6
Author(s):  
Jie Jin ◽  
Xianming Wu ◽  
Zhijun Li
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
Wireless Sensors ◽  
Supply Voltage ◽  
Battery Life ◽  
Ic Design ◽  
Rf Energy Harvesting ◽  
Ultra Low Power ◽  
Rf Energy ◽  
Cmos Rf

An ultra low power mixer with out-of-band radio frequency (RF) energy harvesting suitable for the wireless sensors network (WSN) application is proposed in this paper. The presented mixer is able to harvest the out-of-band RF energy and keep it working in ultra low power condition and extend the battery life of the WSN. The mixer is designed and simulated with Global Foundries ’ 0.18 μ m CMOS RF process, and it operates at 2.4GHz industrial, scientific, and medical (ISM) band. The Cadence IC Design Tools post-layout simulation results demonstrate that the proposed mixer consumes 248 μ W from a 1V supply voltage. Furthermore, the power consumption can be reduced to 120.8 μ W by the out-of-band RF energy harvesting rectifier.

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