2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
Latest Publications

TOTAL DOCUMENTS

101

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Published By IEEE

9781538637661

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Is there a Zero Temperature bias point (ZTC) on Back Enhanced (BE) SOI MOSFET?

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8309258 ◽

2017 ◽

Cited By ~ 3

Author(s):

L. S. Yojo ◽

R. C. Rangel ◽

K. R. A. Sasaki ◽

J. A. Martino

Keyword(s):

Zero Temperature ◽

Soi Mosfet ◽

Temperature Bias ◽

Bias Point

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Reliability analysis on low temperature gate stack process steps for 3D sequential integration

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8309219 ◽

2017 ◽

Author(s):

A. Tsiara ◽

X. Garros ◽

C.-M. V. Lu ◽

C. Fenouillet-Beranger ◽

P. Batude ◽

...

Keyword(s):

Low Temperature ◽

Reliability Analysis ◽

Gate Stack

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A partitioning-free methodology for optimized gate-level monolithic 3D designs

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8309221 ◽

2017 ◽

Cited By ~ 1

Author(s):

O. Billoint ◽

M. Brocard ◽

S. Thuries ◽

G. Berhault ◽

H. Sarhan

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An implementation of 2RW dual-port SRAM using 65 nm Silicon-on-Thin-Box (SOTB) for smart IoT

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8309224 ◽

2017 ◽

Cited By ~ 1

Author(s):

Yoshiki Yamamoto ◽

Takumi Hasegawa ◽

Makoto Yabuuchi ◽

Koji Nii ◽

Yohei Sawada ◽

...

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Analog performance of self-cascode SOI nanowires nMOSFETs aiming at low-power applications

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8309218 ◽

2017 ◽

Author(s):

R. Assalti ◽

M. de Souza ◽

M. Casse ◽

S. Barraud ◽

G. Reimbold ◽

...

Keyword(s):

Low Power ◽

Analog Performance ◽

Self Cascode

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Secured Dual-Rail-Precharge Mux-based (DPMUX) symmetric-logic for low voltage applications

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8309254 ◽

2017 ◽

Cited By ~ 1

Author(s):

David Zooker Zabib ◽

Itamar Levi ◽

Alexander Fish ◽

Osnat Keren

Keyword(s):

Low Voltage

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STT-MRAM for embedded memory applications from eNVM to last level cache

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8308734 ◽

2017 ◽

Author(s):

Luc Thomas ◽

Guenole Jan ◽

Son Le ◽

Santiago Serrano-Guisan ◽

Yuan-Jen Lee ◽

...

Keyword(s):

Embedded Memory ◽

Memory Applications

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New steep-slope device of comprehensive properties enhancement with hybrid operation mechanism for ultra-low-power applications

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8308755 ◽

2017 ◽

Author(s):

Ru Huang ◽

Qianqian Huang ◽

Yang Zhao ◽

Cheng Chen ◽

Rundong Jia ◽

...

Keyword(s):

Low Power ◽

Steep Slope ◽

Ultra Low Power ◽

Operation Mechanism ◽

Comprehensive Properties ◽

Hybrid Operation

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Review of progress in understanding the electron transport properties of amorphous chalcogenide phase change semiconductors (Invited paper)

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8308733 ◽

2017 ◽

Author(s):

Jie Liu

Keyword(s):

Electron Transport ◽

Phase Change ◽

Transport Properties ◽

Amorphous Chalcogenide ◽

Electron Transport Properties

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A 28 nW CMOS supply voltage monitor for adaptive ultra-low power IoT chips

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2017.8344104 ◽

2017 ◽

Author(s):

Divya Akella Kamakshi ◽

Harsh N. Patel ◽

Abhishek Roy ◽

Benton H. Calhoun

Keyword(s):

Low Power ◽

Supply Voltage ◽

Ultra Low Power

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2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Is there a Zero Temperature bias point (ZTC) on Back Enhanced (BE) SOI MOSFET?

Reliability analysis on low temperature gate stack process steps for 3D sequential integration

A partitioning-free methodology for optimized gate-level monolithic 3D designs

An implementation of 2RW dual-port SRAM using 65 nm Silicon-on-Thin-Box (SOTB) for smart IoT

Analog performance of self-cascode SOI nanowires nMOSFETs aiming at low-power applications

Secured Dual-Rail-Precharge Mux-based (DPMUX) symmetric-logic for low voltage applications

STT-MRAM for embedded memory applications from eNVM to last level cache

New steep-slope device of comprehensive properties enhancement with hybrid operation mechanism for ultra-low-power applications

Review of progress in understanding the electron transport properties of amorphous chalcogenide phase change semiconductors (Invited paper)

A 28 nW CMOS supply voltage monitor for adaptive ultra-low power IoT chips

2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
Latest Publications