scholarly journals Fully Integrated Light-Sensing Stimulator Design for Subretinal Implants

Sensors ◽  
2019 ◽  
Vol 19 (3) ◽  
pp. 536 ◽  
Author(s):  
Hosung Kang ◽  
Wajahat Abbasi ◽  
Seong-Woo Kim ◽  
Jungsuk Kim
Keyword(s):  
Low Power ◽  
Ex Vivo ◽  
Incident Light ◽  
Average Power ◽  
Image Sensor ◽  
High Density ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Chip Area ◽  
Fully Integrated

This paper presents a fully integrated photodiode-based low-power and low-mismatch stimulator for a subretinal prosthesis. It is known that a subretinal prosthesis achieves 1600-pixel stimulators on a limited single-chip area that is implanted beneath the bipolar cell layer. However, the high-density pixels cause high power dissipation during stimulation and high fabrication costs because of special process technologies such as the complementary metal-oxide semiconductor CMOS image sensor process. In addition, the many residual charges arising from the high-density pixel stimulation have deleterious effects, such as tissue damage and electrode corrosion, on the retina tissue. In this work, we adopted a switched-capacitor current mirror technique for the single-pixel stimulator (SPStim) that enables low power consumption and low mismatch in the subretinal device. The customized P+/N-well photodiode used to sense the incident light in the SPStim also reduces the fabrication cost. The 64-pixel stimulators are fabricated in a standard 0.35-μm CMOS process along with a global digital controller, which occupies a chip area of 4.3 × 3.2 mm2 and are ex-vivo demonstrated using a dissected pig eyeball. According to measured results, the SPStim accomplishes a maximum biphasic pulse amplitude of 143 μA, which dissipates an average power of 167 μW in a stimulation period of 5 ms, and an average mismatch of 1.12 % between the cathodic and anodic pulses.

scholarly journals Novel Low-Complexity and Low-Power Flip-Flop Design

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 783
Author(s):  
Jin-Fa Lin ◽  
Zheng-Jie Hong ◽  
Chang-Ming Tsai ◽  
Bo-Cheng Wu ◽  
Shao-Wei Yu
Keyword(s):  
Low Power ◽  
Average Power ◽  
Circuit Complexity ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Oxide Semiconductor ◽  
System Level ◽  
Flip Flop ◽  
Chip Area

In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide semiconductor (CMOS) logic to reduce circuit complexity. These circuit optimization measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power, lower leakage power, and smaller layout area; and the transistor-count is only 17. Fabricated in TSMC 180 nm CMOS technology, it reduces by over 29% the chip area compared to the conventional transmission gate FF (TGFF). To further show digital circuit/system level advantages, a multi-mode shift register has been realized. Experimental measurement results at 1.8 V/4 MHz show that, compared with the TGFF design, the proposed design saves 64.7% of power consumption while reducing chip area by 26.2%.

scholarly journals 24 GHz low-power switch-channel CMOS transceiver for wireless localization

2014 ◽  
Vol 7 (6) ◽  
pp. 615-622
Author(s):  
Tao Zhang ◽  
Amin Hamidian ◽  
Ran Shu ◽  
Viswanathan Subramanian
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Continuous Wave ◽  
Noise Figure ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Power Circuit ◽  
Chip Area ◽  
Switch Channel ◽  
24 Ghz

A 24 GHz low-power transceiver is designed, fabricated, and characterized using 130 nm complementary metal-oxide semiconductor (CMOS) process. The designed transceiver is targeted for frequency-modulated-continuous-wave (FMCW) wireless local positioning. The transceiver includes four switchable receiving channels, one transmitting channel and local-oscillator generation circuitries. Several power-saving techniques are implemented, such as switch channel and adaptive mixer biasing. The design aspects of the low-power circuit blocks and integration considerations are presented in details. The integrated transceiver has a chip area of only 2.2 mm × 1.7 mm. In transmitting mode the transceiver achieves an output power of 4 dBm and phase noise of −90 dBc/Hz at 1 MHz, while consuming 75 mW power consumption under 1.5 V power supply. In switch-channel receiving mode the transceiver demonstrates 31 dB gain and 6 dB noise figure with 65 mW power consumption. The transceiver measurements compare well with the simulated results and achieve state-of-the-art performance with very low-power consumption.

A LOW-POWER UWB TRANSCEIVER BY USE OF TRIGGER RECEIVING METHOD

2010 ◽  
Vol 19 (07) ◽  
pp. 1609-1619 ◽  
Author(s):  
SHENG ZHANG ◽  
ZHENG LI ◽  
MENGMENG LIU ◽  
XIAOKANG LIN
Keyword(s):  
Energy Consumption ◽  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Circuit Complexity ◽  
Cmos Process ◽  
Fully Integrated

This paper presents a novel non-coherent receiving algorithm termed trigger receiving algorithm. In comparison with conventional coherent receiving method, the trigger receiving algorithm needs neither local template nor correlation operation, thus both circuit complexity and power consumption are drastically reduced. Based on the proposed algorithm, a fully integrated transceiver was implemented in a 0.18 μ m CMOS process. It occupies an area of 0.44 mm2 and achieves a maximum chip rate of 40 Mbps with 7 mW energy consumption provided by a 1.8 V power supply.

scholarly journals DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW

2019 ◽  
Vol 82 (1) ◽  
Author(s):  
Florence Choong ◽  
Mamun Ibne Reaz ◽  
Mohamad Ibrahim Kamaruzzaman ◽  
Md. Torikul Islam Badal ◽  
Araf Farayez ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Process Technology ◽  
Chip Area ◽  
Digital Phase ◽  
Low Power Dissipation

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL.

scholarly journals A 120-ke− Full-Well Capacity 160-µV/e− Conversion Gain 2.8-µm Backside-Illuminated Pixel with a Lateral Overflow Integration Capacitor

Sensors ◽  
2019 ◽  
Vol 19 (24) ◽  
pp. 5572
Author(s):  
Isao Takayanagi ◽  
Ken Miyauchi ◽  
Shunsuke Okura ◽  
Kazuya Mori ◽  
Junichi Nakamura ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Incident Light ◽  
Complementary Metal Oxide Semiconductor ◽  
Image Sensor ◽  
Oxide Semiconductor ◽  
Conversion Gain ◽  
Cover Glass ◽  
Low Light ◽  
Light Signals ◽  
Backside Illuminated

In this paper, a prototype complementary metal-oxide-semiconductor (CMOS) image sensor with a 2.8-μm backside-illuminated (BSI) pixel with a lateral overflow integration capacitor (LOFIC) architecture is presented. The pixel was capable of a high conversion gain readout with 160 μV/e− for low light signals while a large full-well capacity of 120 ke− was obtained for high light signals. The combination of LOFIC and the BSI technology allowed for high optical performance without degradation caused by extra devices for the LOFIC structure. The sensor realized a 70% peak quantum efficiency with a normal (no anti-reflection coating) cover glass and a 91% angular response at ±20° incident light. This 2.8-μm pixel is potentially capable of higher than 100 dB dynamic range imaging in a pure single exposure operation.

scholarly journals Design of an Edge-Detection CMOS Image Sensor with Built-in Mask Circuits

Sensors ◽  
2020 ◽  
Vol 20 (13) ◽  
pp. 3649
Author(s):  
Minhyun Jin ◽  
Hyeonseob Noh ◽  
Minkyu Song ◽  
Soo Youn Kim
Keyword(s):  
Power Consumption ◽  
Edge Detection ◽  
Low Power ◽  
High Speed ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Frame Rate ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Total Power Consumption

In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm2, and the chip size was 5.15 × 5.15 mm2. The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).

A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs

2019 ◽  
Vol 29 (07) ◽  
pp. 2050108
Author(s):  
Di Li ◽  
Chunlong Fei ◽  
Qidong Zhang ◽  
Yani Li ◽  
Yintang Yang
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Oxide Semiconductor ◽  
Quantization Noise ◽  
Cmos Process ◽  
Noise Shaping ◽  
Signal To Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area

A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.

scholarly journals A Fully Integrated 64-Channel Recording System for Extracellular Raw Neural Signals

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2726
Author(s):  
Xiangwei Zhang ◽  
Quan Li ◽  
Chengying Chen ◽  
Yan Li ◽  
Fuqiang Zuo ◽  
...  
Keyword(s):  
Harmonic Distortion ◽  
Field Potential ◽  
Low Noise ◽  
Recording System ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Cmos Process ◽  
Neural Signals ◽  
Fully Integrated ◽  
Rail To Rail

This paper presents a fully integrated 64-channel neural recording system for local field potential and action potential. It mainly includes 64 low-noise amplifiers, 64 programmable amplifiers and filters, 9 switched-capacitor (SC) amplifiers, and a 10-bit successive approximation register analogue-to-digital converter (SAR ADC). Two innovations have been proposed. First, a two-stage amplifier with high-gain, rail-to-rail input and output, and dynamic current enhancement improves the speed of SC amplifiers. The second is a clock logic that can be used to align the switching clock of 64 channels with the sampling clock of ADC. Implemented in an SMIC 0.18 μm Complementary Metal Oxide Semiconductor (CMOS) process, the 64-channel system chip has a die area of 4 × 4 mm2 and is packaged in a QFN−88 of 10 × 10 mm2. Supplied by 1.8 V, the total power is about 8.28 mW. For each channel, rail-to-rail electrode DC offset can be rejected, the referred-to-input noise within 1 Hz–10 kHz is about 5.5 μVrms, the common-mode rejection ratio at 50 Hz is about 69 dB, and the output total harmonic distortion is 0.53%. Measurement results also show that multiple neural signals are able to be simultaneously recorded.

A read-disturb-free stable low power and high-density GNRFET 6T SRAM with multi-VT technology

Circuit World ◽  
2020 ◽  
Vol 46 (3) ◽  
pp. 203-214
Author(s):  
Pramod Kumar Patel ◽  
M.M. Malik ◽  
Tarun Kumar Gutpa
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Supply Voltage ◽  
Early Stage ◽  
Process Variation ◽  
High Density ◽  
Oxide Semiconductor ◽  
Mass Storage ◽  
Content Type ◽  
Sram Cell

Purpose The performance of the conventional 6T SRAM cell can be improved by using GNRFET devices with multi-threshold technology. The proposed cell shows the strong capability to operate at the minimum supply voltage of 325 mV, whereas the conventional Si-CMOS 6 T SRAM unable to operate below 725 mV, which result in an acceptable failure rate.The advance of Si-CMOS (complementary metal-oxide-semiconductor) based 6 T SRAM cell faces inherent limitation with aggressive downscaling. Hence, there is a need to propose alternatives for the conventional cells. Design/methodology/approach This study aims to improve the performance of the conventional 6T SRAM cell using dual threshold technology, device sizing, optimization of supply voltage under process variation with GNRFET technology. Further performance can be enhanced by resolving half-select issue. Findings The GNRFET-based 6T SRAM cell demonstrates that it is capable of continued improve the performance under the process, voltage, and temperature (PVT) variations significantly better than its CMOS counterpart. Research limitations/implications Nano-material fabrication technology of GNRFETs is in the early stage; hence, the different transistor models can be used to evaluate the parameters of future GNRFETs circuit. Practical implications GNRFET devices are suitable for implementing low power and high density SRAM cell. Social implications The conventional Si-CMOS 6 T SRAM cell is a core component and used as the mass storage element in cache memory in computer system organization, mobile phone and other data storage devices. Originality/value This paper presents a new approach to implement an alternative design of GNRFET -based 6T SRAM cell with doped reservoirs that also supports process variation. In addition, multi-threshold technology optimizes the performance of the proposed cell. The proposed design provides a means to analyze delay and power of GNRFET-based SRAM under process variation with considering edge roughness, and offers design and fabrication insights for cell in the future.

Optimized Design of Low Power Complementary Metal Oxide Semiconductor Low Noise Amplifier for Zigbee Application

2021 ◽  
Vol 18 (4) ◽  
pp. 1327-1330
Author(s):  
S. Manjula ◽  
R. Karthikeyan ◽  
S. Karthick ◽  
N. Logesh ◽  
M. Logeshkumar
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Design System ◽  
Cmos Process ◽  
Design Specifications ◽  
Noise Amplifier

An optimized high gain low power low noise amplifier (LNA) is presented using 90 nm CMOS process at 2.4 GHz frequency for Zigbee applications. For achieving desired design specifications, the LNA is optimized by particle swarm optimization (PSO). The PSO is successfully implemented for optimizing noise figure (NF) when satisfying all the design specifications such as gain, power dissipation, linearity and stability. PSO algorithm is developed in MATLAB to optimize the LNA parameters. The LNA with optimized parameters is simulated using Advanced Design System (ADS) Simulator. The LNA with optimized parameters produces 21.470 dB of voltage gain, 1.031 dB of noise figure at 1.02 mW power consumption with 1.2 V supply voltage. The comparison of designed LNA with and without PSO proves that the optimization improves the LNA results while satisfying all the design constraints.

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