scholarly journals Sensing Responses Based on Transfer Characteristics of InAs Nanowire Field-Effect Transistors

Sensors ◽  
2017 ◽  
Vol 17 (7) ◽  
pp. 1640 ◽  
Author(s):  
Alex Tseng ◽  
David Lynall ◽  
Igor Savelyev ◽  
Marina Blumin ◽  
Shiliang Wang ◽  
...  
2013 ◽  
Vol 25 (15) ◽  
pp. 155303 ◽  
Author(s):  
A Di Bartolomeo ◽  
F Giubileo ◽  
L Iemmo ◽  
F Romeo ◽  
S Santandrea ◽  
...  

2018 ◽  
Vol 20 (11) ◽  
pp. 643-650
Author(s):  
I.I. Abramov ◽  
◽  
N.V. Kolomejtseva ◽  
V.A. Labunov ◽  
I.A. Romanova ◽  
...  

2015 ◽  
Vol 32 (12) ◽  
pp. 127301
Author(s):  
Jun-Da Yan ◽  
Quan Wang ◽  
Xiao-Liang Wang ◽  
Hong-Ling Xiao ◽  
Li-Juan Jiang ◽  
...  

2017 ◽  
Vol 59 (12) ◽  
pp. 2486-2490 ◽  
Author(s):  
A. N. Aleshin ◽  
I. P. Shcherbakov ◽  
I. N. Trapeznikova ◽  
V. N. Petrov

2011 ◽  
Vol 20 (03) ◽  
pp. 653-668 ◽  
Author(s):  
SUPRIYA KARMAKAR ◽  
JOHN A CHANDY ◽  
FAQUIR C. JAIN

This paper describes design of analog-to-digital converters (ADCs) and digital-to-analog onverters (DACs) using field-effect transistors that exhibit three states in their transfer characteristics. An intermediate state " i " has been observed in the transfer characteristics (drain current-gate voltage) of FETs when two layers of cladded quantum dots (e.g. SiO x - Si and GeO x - Ge ) are introduced in the gate region above the tunnel insulator between the source and drain regions. Three states in such a transistor, defined as quantum dot gate field-effect transistor (QDG-FET) include two stable states (ON and OFF) and a low-current saturation state " i " in its transfer characteristics. QDG-FETs are quite different in construction than nanodot based nonvolatile memories, reported in the literature, where the quantum dots are sandwiched between a tunnel gate insulator and a relatively thick control gate dielectric. In this paper we present analog-to-digital converters (ADCs) using comparators based on QDG-FETs. A comparator is designed with fewer three-state QDG-FETs. Designs of 3-bit ADC, using 25 nm QDG-FETs, are simulated showing a signal-to-noise ratio (SNR) of ~18. In addition, the R-2R ladder problem, encountered in conventional analog-to digital converters (ADCs), is absent in QDG-FET based architecture.


2008 ◽  
Vol 93 (15) ◽  
pp. 152104 ◽  
Author(s):  
Ryo Nouchi ◽  
Masashi Shiraishi ◽  
Yoshishige Suzuki

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