scholarly journals FPGA-Based On-Board Hyperspectral Imaging Compression: Benchmarking Performance and Energy Efficiency against GPU Implementations

2020 ◽  
Vol 12 (22) ◽  
pp. 3741 ◽  
Author(s):  
Julián Caba ◽  
María Díaz ◽  
Jesús Barba ◽  
Raúl Guerra ◽  
Jose A. de la Torre and Sebastián López
Keyword(s):  
Reconfigurable Computing ◽  
Power Efficiency ◽  
Real Life ◽  
Hyperspectral Data ◽  
Actual Behavior ◽  
Power Budget ◽  
Image Block ◽  
Power Efficient ◽  
Time Requirements ◽  
Computing Platforms

Remote-sensing platforms, such as Unmanned Aerial Vehicles, are characterized by limited power budget and low-bandwidth downlinks. Therefore, handling hyperspectral data in this context can jeopardize the operational time of the system. FPGAs have been traditionally regarded as the most power-efficient computing platforms. However, there is little experimental evidence to support this claim, which is especially critical since the actual behavior of the solutions based on reconfigurable technology is highly dependent on the type of application. In this work, a highly optimized implementation of an FPGA accelerator of the novel HyperLCA algorithm has been developed and thoughtfully analyzed in terms of performance and power efficiency. In this regard, a modification of the aforementioned lossy compression solution has also been proposed to be efficiently executed into FPGA devices using fixed-point arithmetic. Single and multi-core versions of the reconfigurable computing platforms are compared with three GPU-based implementations of the algorithm on as many NVIDIA computing boards: Jetson Nano, Jetson TX2 and Jetson Xavier NX. Results show that the single-core version of our FPGA-based solution fulfils the real-time requirements of a real-life hyperspectral application using a mid-range Xilinx Zynq-7000 SoC chip (XC7Z020-CLG484). Performance levels of the custom hardware accelerator are above the figures obtained by the Jetson Nano and TX2 boards, and power efficiency is higher for smaller sizes of the image block to be processed. To close the performance gap between our proposal and the Jetson Xavier NX, a multi-core version is proposed. The results demonstrate that a solution based on the use of various instances of the FPGA hardware compressor core achieves similar levels of performance than the state-of-the-art GPU, with better efficiency in terms of processed frames by watt.

scholarly journals Design Space Exploration of High-Performance Parallel Architectures

2008 ◽  
Vol 3 (1) ◽  
pp. 32-38
Author(s):  
Enric Musoll ◽  
Mario Nemirovsky
Keyword(s):  
Power Efficiency ◽  
High Performance ◽  
Design Space Exploration ◽  
Parallel Architecture ◽  
Parallel Architectures ◽  
Power Performance ◽  
Power Budget ◽  
Performance Goal ◽  
Power Efficient ◽  
On Chip

High-performance single-threaded processors achieve their performance goal partly by relying, among other architectural techniques, on speculation and large on-chip caches. The hardware to support these techniques is usually a large portion of the overall processor real state area, and therefore it consumes a significant amount of power that sometimes is not optimally used toward doing useful work. In this work, we study the intuitive fact that architectures with hardware support for threads are more power efficient than a more traditional single-threaded superscalar architecture. Toward this goal, we have created a model of the power, performance and area of several parallel architectures. This model shows that a parallel architecture can be designed so that (a) it requires less area and power (to reach the same performance), or (b) it achieves better power efficiency and less area (for the same power budget), or (c) it has higher performance and better power efficiency (for the same area constraint), when compared to a single-threaded superscalar architecture.

Package Technologies for the 4th Industrial Revolution

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 001095-001117
Author(s):  
Dan Oh
Keyword(s):  
Autonomous Vehicles ◽  
Power Efficiency ◽  
High Performance ◽  
Industrial Revolution ◽  
Early Stage ◽  
Vice President ◽  
Complex Signal ◽  
Mobile Platforms ◽  
Power Efficient ◽  
Computing Platforms

The 4th Industrial Revolution with artificial intelligence, autonomous vehicles, robotics, and biotechnology demands power efficient computing devices such as GPU, TPU, and FPGA. To further enhance the performance, advanced System-in-Package (SiP) such as 2.5D and 3D integration technologies are needed to satisfy the high computing and power efficiency requirements. High-performance SiP systems must integrate advanced packaging technologies with both complex signal/power integrity and enhanced thermal solutions. In addition, package developers need to work closely with chip designers at a very early stage of the product development to achieve the target performance and reliability. In this Keynote, Dr. Oh, Vice President of Package Development at Samsung Electronics will start with an overview of the evolution and importance of package technology to meet the needs of emerging high-end computing platforms. Furthermore, a high-performance SiP system with a Fan Out (FO) package is introduced for power efficient mobile platforms. In addition, the extension of the FO package for high-end server applications is discussed. Finally, pros and cons of the FO package compared to 2.5D Si-interposer are discussed.

Energy Harvesting for Smart Shoes: A Real Life Application

2013 ◽  
Author(s):  
Emanuele Frontoni ◽  
Adriano Mancini ◽  
Primo Zingaretti ◽  
Andrea Gatto
Keyword(s):  
Energy Harvesting ◽  
Power Efficiency ◽  
Indoor Localization ◽  
Electrical Power ◽  
Real Life ◽  
Reducing Power ◽  
Electrical Energy ◽  
General Purpose ◽  
Technical Developments ◽  
Microprocessor Technology

Advanced technical developments have increased the efficiency of devices in capturing trace amounts of energy from the environment (such as from human movements) and transforming them into electrical energy (e.g., to instantly charge mobile devices). In addition, advancements in microprocessor technology have increased power efficiency, effectively reducing power consumption requirements. In combination, these developments have sparked interest in the engineering community to develop more and more applications that utilize energy harvesting for power. The approach here described aims to designing and manufacturing an innovative easy-to-use and general-purpose device for energy harvesting in general purpose shoes. The novelty of this device is the integration of polymer and ceramic piezomaterials accomplished by injection molding. In this spirit, this paper examines different devices that can be built into a shoe, (where excess energy is readily harvested) and used for generating electrical power while walking. A Main purpose is the development of an indoor localization system embedded in shoes that periodically broadcasts a digital RFID as the bearer walks. Results are encouraging and real life test are conducted on the first series of prototypes.

Numerical Modeling of Time-Dependent Deformations of Concrete at 3D Analysis of Structures

2020 ◽  
Author(s):  
◽  
Ante Džolan
Keyword(s):  
Reinforced Concrete ◽  
Prestressed Concrete ◽  
Concrete Structures ◽  
Real Life ◽  
Nonlinear Behavior ◽  
3D Analysis ◽  
Actual Behavior ◽  
Realistic Simulation ◽  
Highly Nonlinear ◽  
Prestressed Structures

Concrete is a material with highly nonlinear behavior. In parallel, there are numerous secondary effects in concrete, such as aging, shrinkage, and creep, which further complicate the realistic simulation of reinforced concrete and prestressed concrete structures. In modern times, due to bolder construction, increasing spans and high rising construction, the need for realistic simulation of the behavior of concrete structures under conditions of various types of loads is becoming more pronounced. On the other hand, models with a small number of real-life parameters that can describe the actual behavior of concrete as accurately as possible are necessary. One such model, the previously developed model Precon 3D, which is based on a small number of parameters and can very well describe the behavior of concrete, reinforced concrete and prestressed structures for short-term static loads was taken as the basis for this work. Through this work, the numerical model Precon 3D has been upgraded with a model for following the behavior of concrete during time, i.e. the model has been upgraded with a model of creep and shrinkage of concrete, which is necessary for following the behavior of prestressed structures. The developed software has been tested against several experimental examples from the literature, with a very good match between numerical and experimental results.

Power-efficient solution-processed red organic light-emitting diodes based on an exciplex host and a novel phosphorescent iridium complex

2016 ◽  
Vol 4 (24) ◽  
pp. 5787-5794 ◽  
Author(s):  
Xuejing Liu ◽  
Bing Yao ◽  
Zilong Zhang ◽  
Xiaofei Zhao ◽  
Baohua Zhang ◽  
...  
Keyword(s):  
Power Efficiency ◽  
Efficient Solution ◽  
Light Emitting Diodes ◽  
Organic Light Emitting Diodes ◽  
Iridium Complex ◽  
Solution Processed ◽  
Power Efficient ◽  
Light Emitting ◽  
Organic Light ◽  
Cie Coordinates

A novel red heteroleptic iridium complex, Ir(DPA-Flpy-CF3)2acac, was synthesized and whose corresponding solution-processed PhOLED shows a record power efficiency of 44.5 lm W−1 with CIE coordinates of (0.64, 0.36).

Customized Hardware Crypto Engine for Wireless Sensor Networks

2017 ◽  
Vol 7 (1) ◽  
pp. 263
Author(s):  
Medhat Awadalla ◽  
Ahmed Al Maashri ◽  
Lavanya Pathuri ◽  
Afaq Ahmad
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Reconfigurable Computing ◽  
Research Area ◽  
Wireless Sensor ◽  
Open Problems ◽  
Algorithmic Approach ◽  
Power Efficient ◽  
Alternative Routing ◽  
Active Research

Nowadays, managing for optimal security to wireless sensor networks (WSNs) has emerged as an active research area. The challenging topics in this active research involve various issues such as energy consumption, routing algorithms, selection of sensors location according to a given premise, robustness, and efficiency. Despite the open problems in WSNs, already a high number of applications available shows the activeness of emerging research in this area. Through this paper, authors propose an alternative routing algorithmic approach that accelerate the existing algorithms in sense to develop a power-efficient crypto system to provide the desired level of security on a smaller footprint, while maintaining real-time performance and mapping them to customized hardware. To achieve this goal, the algorithms have been first analyzed and then profiled to recognize their computational structure that is to be mapped into hardware accelerators in platform of reconfigurable computing devices. An intensive set of experiments have been conducted and the obtained results show that the performance of the proposed architecture based on algorithms implementation outperforms the software implementation running on contemporary CPU in terms of the power consumption and throughput.

scholarly journals Power-Efficient Driver Circuit for Piezo Electric Actuator with Passive Charge Recovery

Energies ◽  
2020 ◽  
Vol 13 (11) ◽  
pp. 2866 ◽  
Author(s):  
Takashi Ozaki ◽  
Norikazu Ohta
Keyword(s):  
Power Consumption ◽  
Piezoelectric Actuator ◽  
Power Efficiency ◽  
Parasitic Capacitance ◽  
Passive Components ◽  
Power Efficient ◽  
Electric Actuator ◽  
Driver Circuit ◽  
Aerial Vehicle ◽  
Charge Recovery

Piezoelectric actuation is a promising principle for insect-scaled robots. A major concern while utilizing a piezoelectric actuator is energy loss due to its parasitic capacitance. In this paper, we propose a new concept to recover the charge stored in the parasitic capacitance; it requires only three additional lightweight passive components: two diodes and a resistor. The advantages of our concept are its small additional mass and simple operating procedure compared with existing charge recovery circuits. We provided a guideline for selecting a resistor using a simplified theoretical model and found that half of the charge can be recovered by employing a resistor that has a resistance sufficiently larger than the forward resistance of the additional diode. In addition, we experimentally demonstrated the concept. With a capacitive load (as a replacement for the piezoelectric actuator), it was successfully observed that the proposed concept decreased the power consumption to 58% of that in a circuit without charge recovery. Considering micro aerial vehicle (MAV) applications, we measured the lift-to-power efficiency of a flapping wing piezoelectric actuator by applying the proposed concept. The lift force was not affected by charge recovery; however, the power consumption was reduced. As a result, the efficiency was improved to 30.0%. We expect that the proposed circuit will contribute to the advancement of energy-saving microrobotics.

scholarly journals A Power-Efficient Soft-Output Detector for Spatial-Multiplexing MIMO Communications

2012 ◽  
Vol 2012 ◽  
pp. 1-9 ◽  
Author(s):  
Hsiao-Chi Wang ◽  
Tung-Lin Liu ◽  
Yuan-Wei Wu ◽  
Hsi-Pin Ma
Keyword(s):  
Power Efficiency ◽  
Search Algorithm ◽  
Power Saving ◽  
Spatial Multiplexing ◽  
Cmos Process ◽  
Tree Search ◽  
Timing Error ◽  
Power Efficient ◽  
Sphere Decoder ◽  
Tree Search Algorithm

VLSI implementation of a configurable power-efficient MIMO detector is proposed to support4×4spatial multiplexing and modulation from QPSK to 64-QAM. A novel tree search algorithm is proposed to enable the detector to provide soft outputs and to be implemented in parallel and pipelined hardware architecture. The frame error rate (FER) of the detector approaches the quasi-optimal sphere decoder, with 0.5-dB degradation. Moreover, the proposed detector can operate at the optimal voltage under different configurations and detect/recover timing error at run time by a novel adaptive voltage scaling technique with double sampling circuitry. The proposed detector, using TSMC 0.18 μm single-poly six-metal CMOS process with a core area of1.17×1.17 mm2, provides fixed throughput of 45 Mbps in 64-QAM configuration, 120 Mbps in 16-QAM configuration, and 60 Mbps in QPSK configuration. The normalized power efficiency of the design for 64-QAM and 16-QAM configurations is 1.56 Mbps/mW and 2.53 Mbps/mW, respectively. Compared with the conservative margin-based design, the proposed design achieves a 48.8% power saving.

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