scholarly journals Iso-Power-Efficiency: An Approach to Scaling Application Codes with a Power Budget

2015 ◽  
Author(s):  
Rogelio Long ◽  
Shirley Moore ◽  
Barry Rountree
Keyword(s):  
Power Efficiency ◽  
Power Budget ◽  
Application Codes

scholarly journals FPGA-Based On-Board Hyperspectral Imaging Compression: Benchmarking Performance and Energy Efficiency against GPU Implementations

2020 ◽  
Vol 12 (22) ◽  
pp. 3741 ◽  
Author(s):  
Julián Caba ◽  
María Díaz ◽  
Jesús Barba ◽  
Raúl Guerra ◽  
Jose A. de la Torre and Sebastián López
Keyword(s):  
Reconfigurable Computing ◽  
Power Efficiency ◽  
Real Life ◽  
Hyperspectral Data ◽  
Actual Behavior ◽  
Power Budget ◽  
Image Block ◽  
Power Efficient ◽  
Time Requirements ◽  
Computing Platforms

Remote-sensing platforms, such as Unmanned Aerial Vehicles, are characterized by limited power budget and low-bandwidth downlinks. Therefore, handling hyperspectral data in this context can jeopardize the operational time of the system. FPGAs have been traditionally regarded as the most power-efficient computing platforms. However, there is little experimental evidence to support this claim, which is especially critical since the actual behavior of the solutions based on reconfigurable technology is highly dependent on the type of application. In this work, a highly optimized implementation of an FPGA accelerator of the novel HyperLCA algorithm has been developed and thoughtfully analyzed in terms of performance and power efficiency. In this regard, a modification of the aforementioned lossy compression solution has also been proposed to be efficiently executed into FPGA devices using fixed-point arithmetic. Single and multi-core versions of the reconfigurable computing platforms are compared with three GPU-based implementations of the algorithm on as many NVIDIA computing boards: Jetson Nano, Jetson TX2 and Jetson Xavier NX. Results show that the single-core version of our FPGA-based solution fulfils the real-time requirements of a real-life hyperspectral application using a mid-range Xilinx Zynq-7000 SoC chip (XC7Z020-CLG484). Performance levels of the custom hardware accelerator are above the figures obtained by the Jetson Nano and TX2 boards, and power efficiency is higher for smaller sizes of the image block to be processed. To close the performance gap between our proposal and the Jetson Xavier NX, a multi-core version is proposed. The results demonstrate that a solution based on the use of various instances of the FPGA hardware compressor core achieves similar levels of performance than the state-of-the-art GPU, with better efficiency in terms of processed frames by watt.

scholarly journals Design Space Exploration of High-Performance Parallel Architectures

2008 ◽  
Vol 3 (1) ◽  
pp. 32-38
Author(s):  
Enric Musoll ◽  
Mario Nemirovsky
Keyword(s):  
Power Efficiency ◽  
High Performance ◽  
Design Space Exploration ◽  
Parallel Architecture ◽  
Parallel Architectures ◽  
Power Performance ◽  
Power Budget ◽  
Performance Goal ◽  
Power Efficient ◽  
On Chip

High-performance single-threaded processors achieve their performance goal partly by relying, among other architectural techniques, on speculation and large on-chip caches. The hardware to support these techniques is usually a large portion of the overall processor real state area, and therefore it consumes a significant amount of power that sometimes is not optimally used toward doing useful work. In this work, we study the intuitive fact that architectures with hardware support for threads are more power efficient than a more traditional single-threaded superscalar architecture. Toward this goal, we have created a model of the power, performance and area of several parallel architectures. This model shows that a parallel architecture can be designed so that (a) it requires less area and power (to reach the same performance), or (b) it achieves better power efficiency and less area (for the same power budget), or (c) it has higher performance and better power efficiency (for the same area constraint), when compared to a single-threaded superscalar architecture.

scholarly journals A Review of Power Management Integrated Circuits for Ultrasound-Based Energy Harvesting in Implantable Medical Devices

2021 ◽  
Vol 11 (6) ◽  
pp. 2487
Author(s):  
Andrea Ballo ◽  
Michele Bottaro ◽  
Alfio Dario Grasso
Keyword(s):  
Energy Harvesting ◽  
Power Management ◽  
Medical Devices ◽  
Power Efficiency ◽  
Building Blocks ◽  
Design Guidelines ◽  
Power Budget ◽  
Implantable Medical Devices ◽  
Piezoelectric Energy ◽  
Piezoelectric Devices

This paper aims to review the recent architectures of power management units for ultrasound-based energy harvesting, while focusing on battery-less implantable medical devices. In such systems, energy sustainability is based on piezoelectric devices and a power management circuit, which represents a key building block since it maximizes the power extracted from the piezoelectric devices and delivers it to the other building blocks of the implanted device. Since the power budget is strongly constrained by the dimension of the piezoelectric energy harvester, complexity of topologies have been increased bit by bit in order to achieve improved power efficiency also in difficult operative conditions. With this in mind, the introduced work consists of a comprehensive presentation of the main blocks of a generic power management unit for ultrasound-based energy harvesting and its operative principles, a review of the prior art and a comparative study of the performance achieved by the considered solutions. Finally, design guidelines are provided, allowing the designer to choose the best topology according to the given design specifications and technology adopted.

Effect of Shielding a Floating Electrode on the Power Efficiency of a Micro-plasma VUV Light Source

2015 ◽  
Vol 135 (3) ◽  
pp. 114-115 ◽  
Author(s):  
Ryoto Sato ◽  
Daisuke Yasumatsu ◽  
Shinya Kumagai ◽  
Masaru Hori ◽  
Minoru Sasaki
Keyword(s):  
Light Source ◽  
Power Efficiency ◽  
Floating Electrode

EXPERIMENTAL AND ANALYTICAL STUDIES OF VERTICAL AXIS WIND TURBINES

2018 ◽  
pp. 51-58
Author(s):  
B. P. Khozyainov
Keyword(s):  
Wind Turbine ◽  
Flow Velocity ◽  
Wind Power ◽  
Wind Turbines ◽  
Power Efficiency ◽  
Air Flow ◽  
Geometrical Parameters ◽  
Wind Speeds ◽  
Analytical Studies ◽  
Air Flow Velocity

The article carries out the experimental and analytical studies of three-blade wind power installation and gives the technique for measurements of angular rate of wind turbine rotation depending on the wind speeds, the rotating moment and its power. We have made the comparison of the calculation results according to the formulas offered with the indicators of the wind turbine tests executed in natural conditions. The tests were carried out at wind speeds from 0.709 m/s to 6.427 m/s. The wind power efficiency (WPE) for ideal traditional installation is known to be 0.45. According to the analytical calculations, wind power efficiency of the wind turbine with 3-bladed and 6 wind guide screens at wind speedsfrom 0.709 to 6.427 is equal to 0.317, and in the range of speed from 0.709 to 4.5 m/s – 0.351, but the experimental coefficient is much higher. The analysis of WPE variations shows that the work with the wind guide screens at insignificant average air flow velocity during the set period of time appears to be more effective, than the work without them. If the air flow velocity increases, the wind power efficiency gradually decreases. Such a good fit between experimental data and analytical calculations is confirmed by comparison of F-test design criterion with its tabular values. In the design of wind turbines, it allows determining the wind turbine power, setting the geometrical parameters and mass of all details for their efficient performance.

TRIPLEPR-MAC: A Triple Queue Priority Based Medium Access Control Protocol for Wireless Sensor Network

2019 ◽  
Vol 09 ◽  
Author(s):  
Rinkuben N. Patel ◽  
Nirav V. Bhatt
Keyword(s):  
Sensor Network ◽  
Data Transmission ◽  
Energy Efficient ◽  
Power Efficiency ◽  
Mac Protocol ◽  
Medium Access Control Protocol ◽  
Quality Factors ◽  
Medium Access ◽  
Critical Fields ◽  
Storage Unit

Background: WSN is a network of smart tiny electromechanical devices named as sensors. Sensors perform various tasks like sensing the environment as per its range, transmit the data using transmission units, store the data in the storage unit and perform an action based on captured data. As they are installed in an unfriendly environment, to recharge the sensors are not possible every time which leads to a limited lifetime of a network. To enhance the life of a sensor network, the network required energy-efficient protocols. Various energy-efficient MAC protocols are developed by Research community, but very few of them are integrated with the priority-based environment which performs the priority-based data transmission. Another challenge of WSN is, most of the WSN areas are delay-sensitive because it is implemented in critical fields like military, disaster management, and health monitoring. Energy, Delay, and throughput are major quality factors that affect the sensor network. Objective: In this paper, the aim is to design and develop a MAC Protocol for a field like the military where the system requires energy efficiency and priority-based data transmission. Method: In the proposed model, the cluster-based network with priority queues are formed that can achieve higher power efficiency and less delay for sensitive data. Results: In this research simulation of Proposed MAC, TMAC and SMAC are done with different numbers of nodes, same inter-packet intervals, and variant inter-packet intervals. Based on the script simulation, result graphs are generated. Conclusion: The proposed work achieves greater lifetime compared to TMAC and SMAC using priority-based data transmission.

Multiple Access using Time Modulated Array with Single RF Chain

2019 ◽  
Vol 12 (5) ◽  
pp. 395-401
Author(s):  
Xu He ◽  
Yuan Ding ◽  
Gaojian Huang
Keyword(s):  
Power Efficiency ◽  
Multiple Access ◽  
Narrow Band ◽  
Average Power ◽  
Access Technology ◽  
Signal Peak ◽  
Single Radio ◽  
Rf Chain ◽  
Synthesis Approach ◽  
Single Rf Chain

Background: A new wireless multiple access technology enabled by using Time Modulated Arrays (TMAs) is proposed in this paper. Methods: It benefits due to the requirement of only a single Radio Frequency (RF) chain, compared with other multiple-RF-chain schemes. Results: As a result, it is able to greatly reduce the system cost, energy consumption, and complexity. Conclusion: In addition, the signal through the single RF chain is narrow-band modulated, reducing the signal Peak-to-Average-Power-Ratio (PAPR), thus, further enhancing the power efficiency of the RF chain, especially for power amplifiers. The operation principle and synthesis approach are elaborated in this paper, and are demonstrated with two examples.

Design Technique of High Power Efficiency LLC DC-DC Converters for Photovoltaic Cells

2018 ◽  
Vol 2 (1) ◽  
pp. 30
Author(s):  
Hisatsugu Kato ◽  
Yoichi Ishizuka ◽  
Kohei Ueda ◽  
Shotaro Karasuyama ◽  
Atsushi Ogasahara
Keyword(s):  
High Power ◽  
Power Efficiency ◽  
Photovoltaic Cells ◽  
Input Voltage ◽  
Design Technique ◽  
Load Range ◽  
Voltage Range ◽  
Simulation Results ◽  
Secondary Side ◽  
High Power Efficiency

This paper proposes a design technique of high power efficiency LLC DC-DC Converters for Photovoltaic Cells. The secondary side circuit and transformer fabrication of proposed circuit are optimized for overcoming the disadvantage of limited input voltage range and, realizing high power efficiency over a wide load range of LLC DC-DC converters. The optimized technique is described with theoretically and with simulation results. Some experimental results have been obtained with the prototype circuit designed for the 80 - 400 V input voltage range. The maximum power efficiency is 98 %.

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