scholarly journals Research and Development of Parameter Extraction Approaches for Memristor Models

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1220
Author(s):  
Dmitry Zhevnenko ◽  
Fedor Meshchaninov ◽  
Vladislav Kozhevnikov ◽  
Evgeniy Shamin ◽  
Oleg Telminov ◽  
...  
Keyword(s):  
Research And Development ◽  
Circuit Design ◽  
Vertical Structure ◽  
Parameter Extraction ◽  
Extraction Methods ◽  
Compact Model ◽  
Design Stage ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
Compact Models

Memristors are among the most promising devices for building neural processors and non-volatile memory. One circuit design stage involves modeling, which includes the option of memristor models. The most common approach is the use of compact models, the accuracy of which is often determined by the accuracy of their parameter extraction from experiment results. In this paper, a review of existing extraction methods was performed and new parameter extraction algorithms for an adaptive compact model were proposed. The effectiveness of the developed methods was confirmed for the volt-ampere characteristic of a memristor with a vertical structure: TiN/HfxAl1-xOy/HfO2/TiN.

scholarly journals A Review for Compact Model of Thin-Film Transistors (TFTs)

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 599 ◽  
Author(s):  
Nianduan Lu ◽  
Wenfeng Jiang ◽  
Quantan Wu ◽  
Di Geng ◽  
Ling Li ◽  
...  
Keyword(s):  
Thin Film ◽  
Circuit Design ◽  
Surface Potential ◽  
Radio Frequency Identification ◽  
Thin Film Transistors ◽  
Parameter Extraction ◽  
Theoretical Description ◽  
Compact Model ◽  
Compact Models ◽  
Identification Tags

Thin-film transistors (TFTs) have grown into a huge industry due to their broad applications in display, radio-frequency identification tags (RFID), logical calculation, etc. In order to bridge the gap between the fabrication process and the circuit design, compact model plays an indispensable role in the development and application of TFTs. The purpose of this review is to provide a theoretical description of compact models of TFTs with different active layers, such as polysilicon, amorphous silicon, organic and In-Ga-Zn-O (IGZO) semiconductors. Special attention is paid to the surface-potential-based compact models of silicon-based TFTs. With the understanding of both the charge transport characteristics and the requirement of TFTs in organic and IGZO TFTs, we have proposed the surface-potential-based compact models and the parameter extraction techniques. The proposed models can provide accurate circuit-level performance prediction and RFID circuit design, and pass the Gummel symmetry test (GST). Finally; the outlook on the compact models of TFTs is briefly discussed.

Power-Fail Detection and Data Storage Design for Control System

2011 ◽  
Vol 383-390 ◽  
pp. 4121-4124
Author(s):  
Liu Min Wang ◽  
Bo Mo
Keyword(s):  
Control System ◽  
Real Time ◽  
Data Storage ◽  
Circuit Design ◽  
Real Time Clock ◽  
Design For Control ◽  
Non Volatile Memory ◽  
System Information ◽  
Volatile Memory ◽  
Information Integrity

The purpose of power-fail protection design is to ensure the certainty and integrity of system information. The key point of design includes: the signals of power-fail detection and data treatm- ent; real-time clock circuit design which is synchronous with the system or as a mark of time; using non-volatile memory (such as FRAM) or using battery backup to maintain trade volatile memory (eg RAM) power to ensure the information integrity and non-volatile storage when the power is removed.

Non-Volatile Memory Devices Based on Diphenyl Bithiophenes

2008 ◽  
Vol 54 ◽  
pp. 458-463
Author(s):  
Eleonora Valeria Canesi ◽  
Chiara Bertarelli ◽  
Andrea Bianco ◽  
M. Caironi ◽  
Giovanni Dassa ◽  
...  
Keyword(s):  
Vertical Structure ◽  
Organic Layer ◽  
Memory Devices ◽  
Conductance Switching ◽  
Non Volatile Memory ◽  
Molecular Origin ◽  
Volatile Memory ◽  
Layer Composition ◽  
Switching Memory

Non volatile memory devices have been developed using diphenyl bithiophene derivatives (DPBT) as active layer. The devices, developed with a two terminal vertical structure where the spin cast organic layer is sandwiched between two electrodes, behave as bistable conductance switching memory cells; the modification of the electrodes material and of the organic layer composition introduces significant changes in the electrical behaviour, that give some indications on the molecular origin of the electrical bistability. These data are enriched by in-situ spectroscopic experiments.

ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory

2015 ◽  
Vol E98.A (12) ◽  
pp. 2494-2504 ◽  
Author(s):  
Masashi TAWADA ◽  
Shinji KIMURA ◽  
Masao YANAGISAWA ◽  
Nozomu TOGAWA
Keyword(s):  
Code Generation ◽  
Non Volatile Memory ◽  
Volatile Memory

Integrated low-temperature process for the fabrication of amorphous Si nanoparticles embedded in Al2 O3 for non-volatile memory application

2016 ◽  
Vol 213 (9) ◽  
pp. 2446-2451 ◽  
Author(s):  
Klemens Ilse ◽  
Thomas Schneider ◽  
Johannes Ziegler ◽  
Alexander Sprafke ◽  
Ralf B. Wehrspohn
Keyword(s):  
Low Temperature ◽  
Si Nanoparticles ◽  
Non Volatile Memory ◽  
Amorphous Si ◽  
Volatile Memory ◽  
Low Temperature Process
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