scholarly journals Improved MRD 4H-SiC MESFET with High Power Added Efficiency

Micromachines ◽  
2019 ◽  
Vol 10 (7) ◽  
pp. 479 ◽  
Author(s):  
Shunwei Zhu ◽  
Hujun Jia ◽  
Xingyu Wang ◽  
Yuan Liang ◽  
Yibo Tong ◽  
...  
Keyword(s):  
Radio Frequency ◽  
Buffer Layer ◽  
High Power ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Design System ◽  
Power Added Efficiency ◽  
Effect Transistor ◽  
Rf Performance

An improved multi-recessed double-recessed p-buffer layer 4H–SiC metal semiconductor field effect transistor (IMRD 4H-SiC MESFET) with high power added efficiency is proposed and studied by co-simulation of advanced design system (ADS) and technology computer aided design (TCAD) Sentaurus software in this paper. Based on multi-recessed double-recessed p-buffer layer 4H–SiC metal semiconductor field effect transistor (MRD 4H-SiC MESFET), the recessed area of MRD MESFET on both sides of the gate is optimized, the direct current (DC), radio frequency (RF) parameters and efficiency of the device is balanced, and the IMRD MESFET with a best power-added efficiency (PAE) is finally obtained. The results show that the PAE of the IMRD MESFET is 68.33%, which is 28.66% higher than the MRD MESFET, and DC and RF performance have not dropped significantly. Compared with the MRD MESFET, the IMRD MESFET has a broader prospect in the field of microwave radio frequency.

scholarly journals An Improved UU-MESFET with High Power Added Efficiency

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 573 ◽  
Author(s):  
Hujun Jia ◽  
Mei Hu ◽  
Shunwei Zhu
Keyword(s):  
Breakdown Voltage ◽  
Threshold Voltage ◽  
High Power ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Drain Current ◽  
Power Added Efficiency ◽  
Effect Transistor ◽  
The Relationship

An improved ultrahigh upper gate 4H-SiC metal semiconductor field effect transistor (IUU-MESFET) is proposed in this paper. The structure is obtained by modifying the ultrahigh upper gate height h of the ultrahigh upper gate 4H-SiC metal semiconductor field effect transistor (UU-MESFET) structure, and the h is 0.1 μm and 0.2 μm for the IUU-MESFET and UU-MESFET, respectively. Compared with the UU-MESFET, the IUU-MESFET structure has a greater threshold voltage and trans-conductance, and smaller breakdown voltage and saturation drain current, and when the ultrahigh upper gate height h is 0.1 μm, the relationship between these parameters is balanced, so as to solve the contradictory relationship that these parameters cannot be improved simultaneously. Therefore, the power added efficiency (PAE) of the IUU-MESFET structure is increased from 60.16% to 70.99% compared with the UU-MESFET, and advanced by 18%.

scholarly journals An Improved 4H-SiC MESFET with a Partially Low Doped Channel

Micromachines ◽  
2019 ◽  
Vol 10 (9) ◽  
pp. 555 ◽  
Author(s):  
Hujun Jia ◽  
Yibo Tong ◽  
Tao Li ◽  
Shunwei Zhu ◽  
Yuan Liang ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
High Power ◽  
Field Effect ◽  
Doping Concentration ◽  
Field Effect Transistor ◽  
Saturation Current ◽  
Absolute Value ◽  
Power Added Efficiency ◽  
Effect Transistor ◽  
The Absolute

An improved 4H-SiC metal semiconductor field effect transistor (MESFET) based on the double-recessed MESFET (DR-MESFET) for high power added efficiency (PAE) is designed and simulated in this paper and its mechanism is explored by co-simulation of ADS and ISE-TCAD software. This structure has a partially low doped channel (PLDC) under the gate, which increases the PAE of the device by decreasing the absolute value of the threshold voltage (Vt), gate-source capacitance (Cgs) and saturation current (Id). The simulated results show that with the increase of H, the PAE of the device increases and then decreases when the value of NPLDC is low enough. The doping concentration and thickness of the PLDC are respectively optimized to be NPLDC = 1 × 1015 cm−3 and H = 0.15 μm to obtain the best PAE. The maximum PAE obtained from the PLDC-MESFET is 43.67%, while the PAE of the DR-MESFET is 23.43%; the optimized PAE is increased by 86.38%.

scholarly journals Improved DRUS 4H-SiC MESFET with High Power Added Efficiency

Micromachines ◽  
2019 ◽  
Vol 11 (1) ◽  
pp. 35
Author(s):  
Hujun Jia ◽  
Yuan Liang ◽  
Tao Li ◽  
Yibo Tong ◽  
Shunwei Zhu ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
High Power ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Space Region ◽  
Saturation Current ◽  
Power Added Efficiency ◽  
Acceptable Range ◽  
Effect Transistor

A 4H-SiC metal semiconductor field effect transistor (MESFET) with layered doping and undoped space regions (LDUS-MESFET) is proposed and simulated by ADS and ISE-TCAD software in this paper. The structure (LDUS-MESFET) introduced layered doping under the lower gate of the channel, while optimizing the thickness of the undoped region. Compared with the double-recessed 4H-SiC MESFET with partly undoped space region (DRUS-MESFET), the power added efficiency of the LDUS-MESFET is increased by 85.8%, and the saturation current is increased by 27.4%. Although the breakdown voltage of the device has decreased, the decrease is within an acceptable range. Meanwhile, the LDUS-MESFET has a smaller gate-source capacitance and a large transconductance. Therefore, the LDUS-MESFET can better balance DC and AC characteristics and improve power added efficiency (PAE).

Temperature Sensitivity Analysis of Extended Source Double Gate Tunnel Field Effect Transistor

2021 ◽  
Author(s):  
Dharmender Nishad ◽  
Kaushal Nigam ◽  
Satyendra Kumar
Keyword(s):  
Temperature Sensitivity ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Of Temperature ◽  
Double Gate ◽  
Extended Source ◽  
Temperature Variations ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

Abstract Temperature-induced performance variation is one of the main concerns of the conventional stack gate oxide double gate tunnel field-effect transistor (SGO-DG-TFET). In this regard, we investigate the temperature sensitivity of extended source double gate tunnel field-effect transistor (ESDG-TFET). For this, we have analyzed the effect of temperature variations on the transfer characteristics, analog/RF, linearity and distortion figure of merits (FOMs) using technology computer aided design (TCAD) simulations. Further, the temperature sensitivity performance is compared with conventional SGO-DG-TFET. The comparative analysis shows that ESDG-TFET is less sensitive to temperature variations compared to the conventional SGO-DG-TFET. Therefore, this indicates that ESDG-TFET is more reliable for low-power, high-frequency applications at a higher temperature compared to conventional SGO-DG-TFET.

scholarly journals Numerical Evaluation of the Effect of Geometric Tolerances on the High-Frequency Performance of Graphene Field-Effect Transistors

Nanomaterials ◽  
2021 ◽  
Vol 11 (11) ◽  
pp. 3121
Author(s):  
Monica La Mura ◽  
Patrizia Lamberti ◽  
Vincenzo Tucci
Keyword(s):  
High Frequency ◽  
Communication Systems ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Channel Length ◽  
Geometrical Parameters ◽  
Effect Transistor ◽  
Rf Performance ◽  
The Impact

The interest in graphene-based electronics is due to graphene’s great carrier mobility, atomic thickness, resistance to radiation, and tolerance to extreme temperatures. These characteristics enable the development of extremely miniaturized high-performing electronic devices for next-generation radiofrequency (RF) communication systems. The main building block of graphene-based electronics is the graphene-field effect transistor (GFET). An important issue hindering the diffusion of GFET-based circuits on a commercial level is the repeatability of the fabrication process, which affects the uncertainty of both the device geometry and the graphene quality. Concerning the GFET geometrical parameters, it is well known that the channel length is the main factor that determines the high-frequency limitations of a field-effect transistor, and is therefore the parameter that should be better controlled during the fabrication. Nevertheless, other parameters are affected by a fabrication-related tolerance; to understand to which extent an increase of the accuracy of the GFET layout patterning process steps can improve the performance uniformity, their impact on the GFET performance variability should be considered and compared to that of the channel length. In this work, we assess the impact of the fabrication-related tolerances of GFET-base amplifier geometrical parameters on the RF performance, in terms of the amplifier transit frequency and maximum oscillation frequency, by using a design-of-experiments approach.

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