scholarly journals Reliability Study of Solder Paste Alloy for the Improvement of Solder Joint at Surface Mount Fine-Pitch Components

Materials ◽  
2014 ◽  
Vol 7 (12) ◽  
pp. 7706-7721 ◽  
Author(s):  
Mohd Rahman ◽  
Noor Zubir ◽  
Raden Leuveano ◽  
Jaharah Ghani ◽  
Wan Mahmood
1999 ◽  
Author(s):  
Jianbiao Pan ◽  
Gregory L. Tonkay

Abstract Stencil printing has been the dominant method of solder deposition in surface mount assembly. With the development of advanced packaging technologies such as ball grid array (BGA) and flip chip on board (FCOB), stencil printing will continue to play an important role. However, the stencil printing process is not completely understood because 52–71 percent of fine and ultra-fine pitch surface mount assembly defects are printing process related (Clouthier, 1999). This paper proposes an analytical model of the solder paste deposition process during stencil printing. The model derives the relationship between the transfer ratio and the area ratio. The area ratio is recommended as a main indicator for determining the maximum stencil thickness. This model explains two experimental phenomena. One is that increasing stencil thickness does not necessarily lead to thicker deposits. The other is that perpendicular apertures print thicker than parallel apertures.


2011 ◽  
Vol 2011 (1) ◽  
pp. 000509-000515 ◽  
Author(s):  
Mary Liu ◽  
Wusheng Yin

With the increasing demand of device miniaturization, high speed, more memory, more function, low cost, and more flexibility in device design and manufacturing chain, YINCAE has published a white paper on a first individual solder joint encapsulant which can eliminate underfilling process with at least five times solder joint increase and provide more flexibility for fine pitch and high density application. In order to meet the demand of manufacturing of high speed and low cost, YINCAE has invented a room temperature stable and jettable solder joint encapsulant adhesive – SMT 266. The invention of SMT 266 has allowed our customers to have more flexibility in their high-speed production line such as worry free on the work life of adhesive and workable jetting process. After being used in the customer field for a few years, the implementation of SMT266 has been approved improving the process yield, eliminating voids and cracks in solder joint, eliminating head-in-pillow issue for large component during lead free reflow process. The results from thermal cycling test indicated that the first failure cycles using SMT266 is high up to 6000 cycles, at least 4000 – 5000 cycles higher than other processes. The pull strength is 1.5 times higher than using solder paste plus underfilling process. All reliability data implied encapsulating each individual solder joint is the right direction to move toward. The enforcement mechanism will be discussed in our paper.


2020 ◽  
Vol 33 (1) ◽  
pp. 20-27
Author(s):  
Sue Teng ◽  
Cherif Guirguis ◽  
Gnyaneshwar Ramakrishna ◽  
Hien Ly

As Cisco’s next-generation products continue to push the trends of higher signal speeds and increased functional density, the need for advanced PCB structures, such as Via-in-Pad Plated Over (VIPPO) and backdrill, and high-speed memory is becoming more mainstream across product platforms.  Furthermore, as these high-speed memory technologies are being driven by consumer applications, the form factor and interconnect pitches continue to shrink to meet the demands of the mobile device market.  The use of these advanced PCB structures, like VIPPO and VIPPO with backdrill, within the BGA footprints, particularly for the fine pitch patterns, have been found to result in BGA solder separation defects at the bulk solder to IMC interface upon a 2nd reflow, e.g. during top-side reflow for bottom-side components or during rework of an adjacent BGA.1  In some cases, this solder separation failure mode has also been identified with buried vias under the BGA pad or even without the presence of VIPPO or any vias under the BGA pad. 2.3 Additionally, these small memory components have been experiencing high occurrences of head-in-pillow (HIP) defects even though the overall package warpage over the reflow profile is < ~3mils. This paper will therefore focus on the mitigation of these solder joint defects resulting from SMT assembly with the use of solder joint encapsulant materials to provide enhanced adhesion strength for the solder joints.  Leveraging existing test vehicles that are known to induce the aforementioned solder joint defects, 2 different solder joint encapsulant or epoxy flux materials are evaluated in terms of the application process, assembly integrity and compatibility with Cisco’s production solder paste materials and SMT processes.


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