scholarly journals A Low-Cost Improved Method of Raw Bit Error Rate Estimation for NAND Flash Memory of High Storage Density

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1900
Author(s):  
Kainan Ma ◽  
Ming Liu ◽  
Tao Li ◽  
Yibo Yin ◽  
Hongda Chen
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Flash Memory ◽  
Low Cost ◽  
Estimation Method ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Storage Density ◽  
Raw Bit Error Rate ◽  
High Storage

Cells wear fast in NAND flash memory of high storage density (HSD), so it is very necessary to have a long-term frequent in-time monitoring on its raw bit error rate (RBER) changes through a fast RBER estimation method. As the flash of HSD already has relatively lower reading speed, the method should not further degrade its read performance. This paper proposes an improved estimation method utilizing known data comparison, includes interleaving to balance the uneven error distribution in the flash of HSD, a fast RBER estimation module to make the estimated RBER highly linearly correlated with the actual RBER, and enhancement strategies to accelerate the decoding convergence of low-density parity-check (LDPC) codes and thereby make up the rate penalty caused by the known data. Experimental results show that when RBER is close to the upper bound of LDPC code, the reading efficiency can be increased by 35.8% compared to the case of no rate penalty. The proposed method only occupies 0.039mm2 at 40nm process condition. Hence, the fast, read-performance-improving, and low-cost method is of great application potential on RBER monitoring in the flash of HSD.

On Die Bit Error Rate Estimator for NAND Flash Memory

2017 ◽  
Vol 64 (7) ◽  
pp. 772-776 ◽  
Author(s):  
Mustafa N. Kaynak ◽  
Patrick R. Khayat ◽  
Sivagnanam Parthasarathy
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory

A High Density and Low Cost Staircase Scheme for 3D NAND Flash Memory: SDS(Stair Divided Scheme)

2019 ◽  
Vol 8 (10) ◽  
pp. P567-P572
Author(s):  
Peizhen Hong ◽  
Zhiliang Xia ◽  
Huaxiang Yin ◽  
Chunlong Li ◽  
Zongliang Huo
Keyword(s):  
Flash Memory ◽  
Low Cost ◽  
High Density ◽  
Nand Flash ◽  
Nand Flash Memory

scholarly journals An SVM-Based NAND Flash Endurance Prediction Method

Micromachines ◽  
2021 ◽  
Vol 12 (7) ◽  
pp. 746
Author(s):  
Haichun Zhang ◽  
Jie Wang ◽  
Zhuo Chen ◽  
Yuqian Pan ◽  
Zhaojun Lu ◽  
...  
Keyword(s):  
Flash Memory ◽  
High Speed ◽  
Low Cost ◽  
Prediction Method ◽  
Machine Learning Algorithms ◽  
Nand Flash ◽  
Transient Faults ◽  
Nand Flash Memory ◽  
Process Improvements ◽  
Noise Interference

NAND flash memory is widely used in communications, commercial servers, and cloud storage devices with a series of advantages such as high density, low cost, high speed, anti-magnetic, and anti-vibration. However, the reliability is increasingly getting worse while process improvements and technological advancements have brought higher storage densities to NAND flash memory. The degradation of reliability not only reduces the lifetime of the NAND flash memory but also causes the devices to be replaced prematurely based on the nominal value far below the minimum actual value, resulting in a great waste of lifetime. Using machine learning algorithms to accurately predict endurance levels can optimize wear-leveling strategies and warn bad memory blocks, which is of great significance for effectively extending the lifetime of NAND flash memory devices and avoiding serious losses caused by sudden failures. In this work, a multi-class endurance prediction scheme based on the SVM algorithm is proposed, which can predict the remaining P-E cycle level and the raw bit error level after various P-E cycles. Feature analysis based on endurance data is used to determine the basic elements of the model. Based on the error features, we present a variety of targeted optimization strategies, such as extracting the numerical features closely related to the endurance, and reducing the noise interference of transient faults through short-term repeated operations. Besides a high-parallel flash test platform supporting multiple protocols, a feature preprocessing module is constructed based on the ZYNQ-7030 chip. The pipelined module of SVM decision model can complete a single prediction within 37 us.

scholarly journals Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1152
Author(s):  
Fei Chen ◽  
Bo Chen ◽  
Hongzhe Lin ◽  
Yachen Kong ◽  
Xin Liu ◽  
...  
Keyword(s):  
Flash Memory ◽  
Temperature Effects ◽  
Memory Systems ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Flash Memories ◽  
Charge Trap ◽  
Fundamental Factor ◽  
Temperature Impacts ◽  
Raw Bit Error Rate

Temperature effects should be well considered when designing flash-based memory systems, because they are a fundamental factor that affect both the performance and the reliability of NAND flash memories. In this work, aiming to comprehensively understanding the temperature effects on 3D NAND flash memory, triple-level-cell (TLC) mode charge-trap (CT) 3D NAND flash memory chips were characterized systematically in a wide temperature range (−30~70 °C), by focusing on the raw bit error rate (RBER) degradation during program/erase (P/E) cycling (endurance) and frequent reading (read disturb). It was observed that (1) the program time showed strong dependences on the temperature and P/E cycles, which could be well fitted by the proposed temperature-dependent cycling program time (TCPT) model; (2) RBER could be suppressed at higher temperatures, while its degradation weakly depended on the temperature, indicating that high-temperature operations would not accelerate the memory cells’ degradation; (3) read disturbs were much more serious at low temperatures, while it helped to recover a part of RBER at high temperatures.

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