A High Density and Low Cost Staircase Scheme for 3D NAND Flash Memory: SDS(Stair Divided Scheme)

2019 ◽  
Vol 8 (10) ◽  
pp. P567-P572
Author(s):  
Peizhen Hong ◽  
Zhiliang Xia ◽  
Huaxiang Yin ◽  
Chunlong Li ◽  
Zongliang Huo
2019 ◽  
Vol 7 ◽  
pp. 1085-1093 ◽  
Author(s):  
Sung-Tae Lee ◽  
Suhwan Lim ◽  
Nag Yong Choi ◽  
Jong-Ho Bae ◽  
Dongseok Kwon ◽  
...  

2020 ◽  
Vol 20 (7) ◽  
pp. 4138-4142
Author(s):  
Sung-Tae Lee ◽  
Suhwan Lim ◽  
Nagyong Choi ◽  
Jong-Ho Bae ◽  
Dongseok Kwon ◽  
...  

NAND flash memory which is mature technology has great advantage in high density and great storage capacity per chip because cells are connected in series between a bit-line and a source-line. Therefore, NAND flash cell can be used as a synaptic device which is very useful for a high-density synaptic array. In this paper, the effect of the word-line bias on the linearity of multi-level conductance steps of the NAND flash cell is investigated. A 3-layer perceptron network (784×200×10) is trained by a suitable weight update method for NAND flash memory using MNIST data set. The linearity of multi-level conductance steps is improved as the word line bias increases from Vth −0.5 to Vth +1 at a fixed bit-line bias of 0.2 V. As a result, the learning accuracy is improved as the word-line bias increases from Vth −0.5 to Vth+1.


Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1900
Author(s):  
Kainan Ma ◽  
Ming Liu ◽  
Tao Li ◽  
Yibo Yin ◽  
Hongda Chen

Cells wear fast in NAND flash memory of high storage density (HSD), so it is very necessary to have a long-term frequent in-time monitoring on its raw bit error rate (RBER) changes through a fast RBER estimation method. As the flash of HSD already has relatively lower reading speed, the method should not further degrade its read performance. This paper proposes an improved estimation method utilizing known data comparison, includes interleaving to balance the uneven error distribution in the flash of HSD, a fast RBER estimation module to make the estimated RBER highly linearly correlated with the actual RBER, and enhancement strategies to accelerate the decoding convergence of low-density parity-check (LDPC) codes and thereby make up the rate penalty caused by the known data. Experimental results show that when RBER is close to the upper bound of LDPC code, the reading efficiency can be increased by 35.8% compared to the case of no rate penalty. The proposed method only occupies 0.039mm2 at 40nm process condition. Hence, the fast, read-performance-improving, and low-cost method is of great application potential on RBER monitoring in the flash of HSD.


Micromachines ◽  
2021 ◽  
Vol 12 (7) ◽  
pp. 746
Author(s):  
Haichun Zhang ◽  
Jie Wang ◽  
Zhuo Chen ◽  
Yuqian Pan ◽  
Zhaojun Lu ◽  
...  

NAND flash memory is widely used in communications, commercial servers, and cloud storage devices with a series of advantages such as high density, low cost, high speed, anti-magnetic, and anti-vibration. However, the reliability is increasingly getting worse while process improvements and technological advancements have brought higher storage densities to NAND flash memory. The degradation of reliability not only reduces the lifetime of the NAND flash memory but also causes the devices to be replaced prematurely based on the nominal value far below the minimum actual value, resulting in a great waste of lifetime. Using machine learning algorithms to accurately predict endurance levels can optimize wear-leveling strategies and warn bad memory blocks, which is of great significance for effectively extending the lifetime of NAND flash memory devices and avoiding serious losses caused by sudden failures. In this work, a multi-class endurance prediction scheme based on the SVM algorithm is proposed, which can predict the remaining P-E cycle level and the raw bit error level after various P-E cycles. Feature analysis based on endurance data is used to determine the basic elements of the model. Based on the error features, we present a variety of targeted optimization strategies, such as extracting the numerical features closely related to the endurance, and reducing the noise interference of transient faults through short-term repeated operations. Besides a high-parallel flash test platform supporting multiple protocols, a feature preprocessing module is constructed based on the ZYNQ-7030 chip. The pipelined module of SVM decision model can complete a single prediction within 37 us.


2014 ◽  
Vol 53 (4S) ◽  
pp. 04ED17
Author(s):  
Takeshi Sasaki ◽  
Masakazu Muraguchi ◽  
Moon-Sik Seo ◽  
Sung-kye Park ◽  
Tetsuo Endoh

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