Program error rate-based wear leveling for NAND flash memory

2018 ◽  
Author(s):  
Xin Shi ◽  
Fei Wu ◽  
Shunzhuo Wang ◽  
Changsheng Xie ◽  
Zhonghai Lu
Keyword(s):  
Error Rate ◽  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Wear Leveling ◽  
Program Error

scholarly journals A Block Classification Method with Monitor and Restriction in NAND Flash memory

2021 ◽  
Vol 12 (5) ◽  
pp. 209-215
Author(s):  
Myungsub Lee
Keyword(s):  
Performance Evaluation ◽  
Standard Deviation ◽  
Flash Memory ◽  
Garbage Collection ◽  
Memory Systems ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Wear Leveling ◽  
Block Classification ◽  
Update Frequency

In this paper, we propose a block classification with monitor and restriction (BCMR) method to isolate and reduce the interference of blocks in garbage collection and wear leveling. The proposed method monitors the endurance variation of blocks during garbage collection and detects hot blocks by making a restriction condition based on this information. This method induces block classification by its update frequency for garbage collection and wear leveling, resulting in a prolonged lifespan for NAND flash memory systems. The performance evaluation results show that the BCMR method prolonged the life of NAND flash memory systems by 3.95% and reduced the standard deviation per block by 7.4%, on average.

SREA: A self-recovery effect aware wear-leveling strategy for the reliability extension of NAND flash memory

2019 ◽  
Vol 100-101 ◽  
pp. 113433 ◽  
Author(s):  
Debao Wei ◽  
Liyan Qiao ◽  
Xiaoyu Chen ◽  
Mengqi Hao ◽  
Xiyuan Peng
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Recovery Effect ◽  
Nand Flash Memory ◽  
Wear Leveling

On Die Bit Error Rate Estimator for NAND Flash Memory

2017 ◽  
Vol 64 (7) ◽  
pp. 772-776 ◽  
Author(s):  
Mustafa N. Kaynak ◽  
Patrick R. Khayat ◽  
Sivagnanam Parthasarathy
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory

scholarly journals A Low-Cost Improved Method of Raw Bit Error Rate Estimation for NAND Flash Memory of High Storage Density

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1900
Author(s):  
Kainan Ma ◽  
Ming Liu ◽  
Tao Li ◽  
Yibo Yin ◽  
Hongda Chen
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Flash Memory ◽  
Low Cost ◽  
Estimation Method ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Storage Density ◽  
Raw Bit Error Rate ◽  
High Storage

Cells wear fast in NAND flash memory of high storage density (HSD), so it is very necessary to have a long-term frequent in-time monitoring on its raw bit error rate (RBER) changes through a fast RBER estimation method. As the flash of HSD already has relatively lower reading speed, the method should not further degrade its read performance. This paper proposes an improved estimation method utilizing known data comparison, includes interleaving to balance the uneven error distribution in the flash of HSD, a fast RBER estimation module to make the estimated RBER highly linearly correlated with the actual RBER, and enhancement strategies to accelerate the decoding convergence of low-density parity-check (LDPC) codes and thereby make up the rate penalty caused by the known data. Experimental results show that when RBER is close to the upper bound of LDPC code, the reading efficiency can be increased by 35.8% compared to the case of no rate penalty. The proposed method only occupies 0.039mm2 at 40nm process condition. Hence, the fast, read-performance-improving, and low-cost method is of great application potential on RBER monitoring in the flash of HSD.

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