scholarly journals Gallium Nitride Normally Off MOSFET Using Dual-Metal-Gate Structure for the Improvement in Current Drivability

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1402
Author(s):  
Young Jun Yoon ◽  
Jae Sang Lee ◽  
Dong-Seok Kim ◽  
Jung-Hee Lee ◽  
In Man Kang
Keyword(s):  
Gallium Nitride ◽  
Carrier Transport ◽  
High Efficiency ◽  
Oxide Semiconductor ◽  
Electron Velocity ◽  
Metal Gate ◽  
Dual Metal ◽  
Current Characteristics ◽  
Work Function Difference ◽  
Recessed Gate

A gallium nitride (GaN)-based normally off metal–oxide–semiconductor field-effect transistor (MOSFET) using a dual-metal-gate (DMG) structure was proposed and fabricated to improve current drivability. Normally off operation with a high Vth of 2.3 V was obtained using a Cl2/BCl3-based recess etching process. The DMG structure was employed to improve current characteristics, which can be degraded by recess etching. The ID and gm of a DMG-based device with nickel (Ni)-aluminum (Al) were improved by 42.1% and 30.9%, respectively, in comparison to the performances of a single-metal-gate-based device with Ni because the DMG structure increased electron velocity in the channel region. This demonstrates that the DMG structure with a large work-function difference significantly improves the carrier transport efficiency. GaN-based recessed-gate MOSFETs based on the DMG structure hold promising potentials for high-efficiency power devices.

Leakage current characteristics in MOCVD grown InAs quantum dot embedded GaAs metal-oxide-semiconductor capacitor

RSC Advances ◽  
2015 ◽  
Vol 5 (102) ◽  
pp. 83837-83842 ◽  
Author(s):  
Sk Masiul Islam ◽  
K. Sarkar ◽  
P. Banerji ◽  
Kalyan Jyoti Sarkar ◽  
Biswajit Pal
Keyword(s):  
Quantum Dot ◽  
Leakage Current ◽  
Carrier Transport ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Embedded Devices ◽  
Mos Capacitors ◽  
Current Characteristics ◽  
Inas Quantum Dot ◽  
Metal Oxide Semiconductor Capacitor

Carrier transport vis-a-vis leakage current in GaAs MOS capacitors with various structures; quantum dot embedded devices show the lowest leakage.

Work Function Modulation by Segregation of Indium through Tungsten Gate for Dual-Metal-Gate Complementary Metal Oxide Semiconductor Applications

2007 ◽  
Vol 46 (4B) ◽  
pp. 1885-1887 ◽  
Author(s):  
Kazuaki Nakajima ◽  
Masato Koyama ◽  
Tomonori Aoyama ◽  
Akira Nishiyama ◽  
Kazuhiro Eguchi ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Work Function ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Metal Gate ◽  
Dual Metal

scholarly journals Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology

2009 ◽  
Vol 2009 ◽  
pp. 1-10 ◽  
Author(s):  
Wu-Te Weng ◽  
Yao-Jen Lee ◽  
Horng-Chih Lin ◽  
Tiao-Yuan Huang
Keyword(s):  
Metal Oxide ◽  
Gate Dielectric ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Metal Gate ◽  
Metal Gates ◽  
Bias Temperature Instability ◽  
Dual Metal

This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.

Metal Wet Etch Process Development for Dual Metal Gate CMOS

2005 ◽  
Vol 8 (12) ◽  
pp. G333 ◽  
Author(s):  
Muhammad Mustafa Hussain ◽  
Naim Moumen ◽  
Joel Barnett ◽  
Jason Saulters ◽  
David Baker ◽  
...  
Keyword(s):  
Process Development ◽  
Metal Gate ◽  
Dual Metal ◽  
Wet Etch

scholarly journals Complete Ring Artifacts Reduction Procedure for Lab-Based X-ray Nano CT Systems

Sensors ◽  
2021 ◽  
Vol 21 (1) ◽  
pp. 238
Author(s):  
Jakub Šalplachta ◽  
Tomáš Zikmund ◽  
Marek Zemek ◽  
Adam Břínek ◽  
Yoshihiro Takeda ◽  
...  
Keyword(s):  
High Efficiency ◽  
Image Inpainting ◽  
Simulated Data ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Detection Accuracy ◽  
Reduction Procedure ◽  
X Ray ◽  
Artifacts Reduction ◽  
Ct Data

In this article, we introduce a new ring artifacts reduction procedure that combines several ideas from existing methods into one complex and robust approach with a goal to overcome their individual weaknesses and limitations. The procedure differentiates two types of ring artifacts according to their cause and character in computed tomography (CT) data. Each type is then addressed separately in the sinogram domain. The novel iterative schemes based on relative total variations (RTV) were integrated to detect the artifacts. The correction process uses the image inpainting, and the intensity deviations smoothing method. The procedure was implemented in scope of lab-based X-ray nano CT with detection systems based on charge-coupled device (CCD) and scientific complementary metal–oxide–semiconductor (sCMOS) technologies. The procedure was then further tested and optimized on the simulated data and the real CT data of selected samples with different compositions. The performance of the procedure was quantitatively evaluated in terms of the artifacts’ detection accuracy, the comparison with existing methods, and the ability to preserve spatial resolution. The results show a high efficiency of ring removal and the preservation of the original sample’s structure.

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