A 2.5 GHz low noise high linearity LNA/mixer IC in SiGe BiCMOS technology

Author(s):  
D. Wang ◽  
K. Krishnamurthi ◽  
S. Gibson ◽  
J. Brunt
Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 831 ◽  
Author(s):  
Jingyu Han ◽  
Yu Jiang ◽  
Guiliang Guo ◽  
Xu Cheng

A highly reconfigurable open-loop analog baseband circuitry with programmable gain, bandwidth and filter order are proposed for integrated linear frequency modulated continuous wave (LFMCW) radar receivers in this paper. This analog baseband chain allocates noise, gain and channel selection specifications to different stages, for the sake of noise and linearity tradeoffs, by introducing a multi-stage open-loop cascaded amplifier/filter topology. The topology includes a course gain tuning pre-amplifier, a folded Gilbert variable gain amplifier (VGA) with a symmetrical dB-linear voltage generator and a 10-bit R-2R DAC for fine gain tuning, a level shifter, a programmable Gm-C low pass filter, a DC offset cancellation circuit, two fixed gain amplifiers with bandwidth extension and a novel buffer amplifier with active peaking for testing purposes. The noise figure is reduced with the help of a low noise pre-amplifier stage, while the linearity is enhanced with a power-efficient buffer and a novel high linearity Gm-C filter. Specifically, the Gm-C filter improves its linearity specification with no increase in power consumption, thanks to an alteration of the trans-conductor/capacitor connection style, instead of pursuing high linearity but power-hungry class-AB trans-conductors. In addition, the logarithmic bandwidth tuning technique is adopted for capacitor array size minimization. The linear-in-dB and DAC gain control topology facilitates the analog baseband gain tuning accuracy and stability, which also provides an efficient access to digital baseband automatic gain control. The analog baseband chip is fabricated using 130-nm SiGe BiCMOS technology. With a power consumption of 5.9~8.8 mW, the implemented circuit achieves a tunable gain range of −30~27 dB (DAC linear gain step guaranteed), a programmable −3 dB bandwidth of 18/19/20/21/22/23/24/25 MHz, a filter order of 3/6 and a gain resolution of better than 0.07 dB.


2013 ◽  
Vol 380-384 ◽  
pp. 3287-3291
Author(s):  
Bing Liang Yu ◽  
Xiao Ning Xie ◽  
Wen Yuan Li

A fully integrated low noise amplifier (LNA) for wireless local area network (WLAN) application is presents. The circuit is fabricated in 0.18μm SiGe BiCMOS technology. For the low noise figure, a feedback path is introduced into the traditional inductively degenerated common emitter cascade LNA, which decreases the inductance for input impedance matching, therefore reduces the thermal noise caused by loss resistor. Impedance matching and noise matching are achieved at the same time. Measured results show that the resonance point of the output resonance network shifts from 2.4GHz to 2.8GHz, due to the parasitic effects at the output. At the frequency of 2.8GHz, the LNA achieves 2.2dB noise figure, 19.4dB power gain. The core circuit consumes only 13mW from a 1.8V supply and occupies less than 0.5mm2.


Author(s):  
V.J. Patel ◽  
H.S. Axtell ◽  
C.L. Cerny ◽  
G.L. Creech ◽  
R.G. Drangmeister ◽  
...  

2011 ◽  
Vol 130-134 ◽  
pp. 3267-3271
Author(s):  
Kang Li ◽  
Chao Xian Zhu ◽  
Xiao Feng Yang ◽  
Qian Feng ◽  
Chi Liu ◽  
...  

A 2.4GHz high linearity downconversion mixer is designed with MOSFET transconductance linearization technique. Multiple gated transistors (MGTR) (or derivative superposition) method is adopted in the structure to increase IIP3 of the mixer as well as its convertion gain isn’t degraded. In order to improve the performance of the mixer further, a LC tank is used in the LO stage and two current steering PMOS transistors in load stage. The Mixer is design in TSMC 0.35um SiGe BiCMOS technology. Simulation results show that the mixer achieves 2.88dBm input 1dB compress point, 16.18dBm third-order input intercept point (IIP3) and the conversion gain is 12.97dB.


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