scholarly journals Enabling ISO 26262 Compliance with Accelerated Diagnostic Coverage Assessment

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 732
Author(s):  
Frederico Ferlini ◽  
Laio Oriel Seman ◽  
Eduardo Augusto Bezerra
Keyword(s):  
Development Process ◽  
Fault Injection ◽  
Functional Verification ◽  
Description Language ◽  
Automotive Safety ◽  
Iso 26262 ◽  
Safety Integrity Level ◽  
Hardware Description ◽  
Small Parts ◽  
Vehicle Development Process

Modern vehicles are integrating a growing number of electronics to provide a safer experience for the driver. Therefore, safety is a non-negotiable requirement that must be considered through the vehicle development process. The ISO 26262 standard provides guidance to ensure that such requirements are implemented. Fault injection is highly recommended for the functional verification of safety mechanisms or to evaluate their diagnostic coverage capability. An exhaustive analysis is not required, but evidence of best effort through the diagnostic coverage assessment needs to be provided when performing quantitative evaluation of hardware architectural metrics. These metrics support that the automotive safety integrity level—ranging from A (lowest) to D (strictest) levels—was obeyed. In this context, this paper proposed a verification solution in order to build an approach that can accelerate the diagnostic coverage assessment via fault injection in the semiconductor level (i.e., hardware description language). The proposed solution does not require any modification of the design model to enable acceleration. Small parts of the OpenRISC architecture (namely a carry adder, the Tick Timer peripheral, and the exception block) were used to illustrate the methodology.

ISO 26262 Concept Phase Analysis on Distributed Electro-Hydraulic Braking System: The Influence of System Architecture on ASIL Decomposition

2014 ◽  
Author(s):  
Zhizhong Wang ◽  
Liangyao Yu ◽  
Ning Pan ◽  
Lei Zhang ◽  
Jian Song
Keyword(s):  
System Architecture ◽  
Event Analysis ◽  
Automotive Safety ◽  
System Architectures ◽  
Iso 26262 ◽  
Braking System ◽  
Safety Integrity Level ◽  
Actuator System ◽  
Hazardous Event ◽  
Wire System

The Distributed Electro-hydraulic Braking system (DEHB) is a wet type brake-by-wire system. As a safety critical automotive electrical and/or electronic (E/E) system, DEHB shall be designed under the guideline of ISO 26262 in order to avoid unreasonable risk due to the malfunctions in the item. This paper explores how the Automotive Safety Integrity Level (ASIL) decomposition in the concept phase is influenced by the system architectures of DEHB. Based on a typical hazardous event, analysis on DEHB with the same system architecture as the Electro-mechanical Braking system (EMB) is carried out, which is taken as the basis for comparison. Two types of DEHB with different system architectures are then analyzed. Results show that the adoption of hydraulic backup enables ASIL decomposition in the pedal unit. The adoption of both hydraulic backup and normally open balance valves offers the opportunity to perform ASIL decomposition in the brake actuator system of DEHB.

scholarly journals Fine-Grain Circuit Hardening Through VHDL Datatype Substitution

Electronics ◽  
2018 ◽  
Vol 8 (1) ◽  
pp. 24 ◽  
Author(s):  
Maria Muñoz-Quijada ◽  
Samuel Sanchez-Barea ◽  
Daniel Vela-Calderon ◽  
Hipolito Guzman-Miranda
Keyword(s):  
Radiation Effects ◽  
Digital Circuits ◽  
Fault Injection ◽  
Description Language ◽  
New Approach ◽  
Internal Memory ◽  
Fine Grain ◽  
Radiation Induced ◽  
Hardware Description ◽  
Modular Redundancy

Radiation effects can induce, amongst other phenomena, logic errors in digital circuits and systems. These logic errors corrupt the states of the internal memory elements of the circuits and can propagate to the primary outputs, affecting other onboard systems. In order to avoid this, Triple Modular Redundancy is typically used when full robustness against these phenomena is needed. When full triplication of the complete design is not required, selective hardening can be applied to the elements in which a radiation-induced upset is more likely to propagate to the main outputs of the circuit. The present paper describes a new approach for selectively hardening digital electronic circuits by design, which can be applied to digital designs described in the VHDL Hardware Description Language. When the designer changes the datatype of a signal or port to a hardened type, the necessary redundancy is automatically inserted. The automatically hardening features have been compiled into a VHDL package, and have been validated both in simulation and by means of fault injection.

Hardware-in-the-Loop Simulation of Functional Safety Compliant Electric Power Steering System

2015 ◽  
Vol 781 ◽  
pp. 500-503
Author(s):  
Kyung Jung Lee ◽  
Hyun Sik Ahn
Keyword(s):  
Electric Power ◽  
Steering System ◽  
Functional Safety ◽  
Hardware In The Loop ◽  
Electric Power Steering ◽  
Automotive Safety ◽  
Iso 26262 ◽  
Power Steering ◽  
Safety Integrity Level ◽  
Electric Power Steering System

In this paper, we propose a hardware-in-the-loop simulation (HILS) for functional safety compliant electric power steering (EPS) system. The proliferation of electric and electronic systems in vehicles has brought the new automotive standard ISO 26262 for the safety of functions. The proposed EPS system should be Automotive Safety Integrity Level (ASIL) D compliant, which is the highest ASIL level. Therefore, EPS system complies with functional safety and HILS is configured to verify performance of functional safety compliant EPS system.

scholarly journals Functional Safety BMS Design Methodology for Automotive Lithium-Based Batteries

Energies ◽  
2021 ◽  
Vol 14 (21) ◽  
pp. 6942
Author(s):  
David Marcos ◽  
Maitane Garmendia ◽  
Jon Crego ◽  
José Antonio Cortajarena
Keyword(s):  
Design Methodology ◽  
International Standards ◽  
Automotive Application ◽  
Special Focus ◽  
Battery Management ◽  
Functional Safety ◽  
Automotive Safety ◽  
Iso 26262 ◽  
Safety Integrity Level ◽  
Hazard And Risk

The increasing use of lithium batteries and the necessary integration of battery management systems (BMS) has led international standards to demand functional safety in electromobility applications, with a special focus on electric vehicles. This work covers the complete design of an enhanced automotive BMS with functional safety from the concept phase to verification activities. Firstly, a detailed analysis of the intrinsic hazards of lithium-based batteries is performed. Secondly, a hazard and risk assessment of an automotive lithium-based battery is carried out to address the specific risks deriving from the automotive application and the safety goals to be fulfilled to keep it under control. Safety goals lead to the technical safety requirements for the next hardware design and prototyping of a BMS Slave. Finally, the failure rate of the BMS Slave is assessed to verify the compliance of the developed enhanced BMS Slave with the functional safety Automotive Safety Integrity Level (ASIL) C. This paper contributes the design methodology of a BMS complying with ISO 26262 functional safety standard requirements for automotive lithium-based batteries.

AUTOMATED DEBUGGING OF VERILOG DESIGNS

2012 ◽  
Vol 22 (05) ◽  
pp. 695-723 ◽  
Author(s):  
BERNHARD PEISCHL ◽  
NAVEED RIAZ ◽  
FRANZ WOTAWA
Keyword(s):  
Development Process ◽  
Hardware Description Language ◽  
Working Process ◽  
Description Language ◽  
Root Cause ◽  
Software Debugging ◽  
Hardware Description ◽  
Description Languages ◽  
Novel Model ◽  
Test Suites

In this article we report on novel insights in model-based software debugging of hardware description languages (HDLs). Today's simulation driven working process emphasizes the need for exploiting test suites not only for detecting but also for localizing the root cause of misbehavior. We discuss the modeling approaches for the various artifacts of the Verilog hardware description language (blocking and non-blocking statements, expressions, execution ordering) and present a novel model incorporating test suites. The evaluation of our approach on the well-known ISCAS89 benchmarks concerning single and double-fault diagnoses clearly indicates that incorporating test suites into the fault localization technique (and development process) considerably improves the accuracy of the obtained diagnosis candidates.

Performance Analysis of an Area Efficient and Low Power MOD-R2MDC FFT for MIMO OFDM

2014 ◽  
Vol 573 ◽  
pp. 176-180
Author(s):  
G. Kavitha ◽  
B. Kirthiga ◽  
N. Kirubanandasarathy
Keyword(s):  
Low Power ◽  
Orthogonal Frequency Division Multiplexing ◽  
Ofdm System ◽  
Description Language ◽  
Fft Processor ◽  
Synthesis Tool ◽  
Mimo Ofdm ◽  
Hardware Description ◽  
Fft Algorithms ◽  
Area Efficient

In this paper, an area-efficient low power fast fourier transform (FFT) processor is proposed for multi input multi output-orthogonal frequency division multiplexing (MIMO-OFDM) in wireless communication system. It consists of a modified architecture of radix-2 algorithm which is described as modified radix-2 multipath delay commutation (MOD-R2MDC). The OFDM receiver with modified R2MDC (MOD-R2MDC) FFT was designed by Hardware Description Language (HDL) coding The Xilinx ISE Design Suite 10.1 is used as a synthesis tool for getting the power and area. The Model-Sim 6.3c is used for simulation. Also the existing OFDM system has been tested with these FFT algorithms and their performances were analyzed with respect to occupancy area in FPGA and power consumption. A low-power and area efficient architecture enables the real-time operations of MIMO OFDM system.

Hierarchical Configurable Petri Net Modeling in VHDL

2012 ◽  
Vol 58 (4) ◽  
pp. 397-402 ◽  
Author(s):  
Michał Doligalski ◽  
Marian Adamski
Keyword(s):  
Petri Nets ◽  
Petri Net ◽  
Control Process ◽  
Discrete Control ◽  
Dual Model ◽  
Description Language ◽  
Direct Support ◽  
Hardware Description ◽  
Logical Synthesis ◽  
State Machine Diagram

Abstract The paper presents method for hierarchical configurable Petri nets description in VHDL language. Dual model is an alternative way for behavioral description of the discrete control process. Dual model consists of two correlated models: UML state machine diagram and hierarchical configurable Petri net (HCfgPN). HCfgPN are Petri nets variant with direct support of exceptions handling mechanism. Logical synthesis of dual model is realized by the description of HCfgPN model by means of hardware description language. The paper presents placesoriented method for HCfgPN description in VHDL language

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