scholarly journals Time-Encoding-Based Ultra-Low Power Features Extraction Circuit for Speech Recognition Tasks

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 418
Author(s):  
Eric Gutierrez ◽  
Carlos Perez ◽  
Fernando Hernandez ◽  
Luis Hernandez
Keyword(s):  
Feature Extraction ◽  
Speech Recognition ◽  
Power Consumption ◽  
Low Power ◽  
System Level ◽  
Portable Devices ◽  
Cmos Process ◽  
Ring Oscillators ◽  
Ultra Low Power ◽  
Band Pass

Current trends towards on-edge computing on smart portable devices requires ultra-low power circuits to be able to make feature extraction and classification tasks of patterns. This manuscript proposes a novel approach for feature extraction operations in speech recognition/voice activity detection tasks suitable for portable devices. Whereas conventional approaches are based on either completely analog or digital structures, we propose a “hybrid” approach by means of voltage-controlled-oscillators. Our proposal makes use of a bank a band-pass filters implemented with ring-oscillators to extract the features (energy within different frequency bands) of input audio signals and digitize them. Afterwards, these data will input a digital classification stage such as a neural network. Ring-oscillators are structures with a digital nature, which makes them highly scalable with the possibility of designing them with minimum length devices. Additionally, due to their inherent phase integration, low-frequency band-pass filters can be implemented without large capacitors. Consequently, we strongly benefit from power consumption and area savings. Finally, our proposal may incorporate the analog-to-digital converter into the structure of the own features extractor circuit to make the full conversion of the raw data when triggered. This supposes a unique advantage with respect to other approaches. The architecture is described and proposed at system-level, along with behavioral simulations made to check whether the performance is the expected one or not. Then the structure is designed with a 65-nm CMOS process to estimate the power consumption and area on a silicon implementation. The results show that our solution is very promising in terms of occupied area with a competitive power consumption in comparison to other state-of-the-art solutions.

scholarly journals Subthreshold Region based Linear Feedback Shift Register

2019 ◽  
Vol 8 (6S2) ◽  
pp. 817-821
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
System Level ◽  
Linear Feedback ◽  
Portable Devices ◽  
Subthreshold Region ◽  
Flip Flop ◽  
Ultra Low Power

Growing demand for portable devices and fast increases in complexity of chip cause power dissipation is an important parameter. Power consumption and dissipation or generations of more heat possess a restriction in the direction of the integration of more transistors. Several methods have been proposed to reduce power dissipation from system level to device level. Subthreshold circuits are widely used in more advanced applications due to ultra low-power consumption. The present work targets on construction of linear feedback shift registers (LFSR) in weak inversion region and their performance observed in terms of parameters like power delay product (PDP). In CMOS circuits subthreshold region of operation allows a low-power for ample utilizations but this advantage get with the penalty of flat speed. For the entrenched and high speed applications, improving the speed of subthreshold designs is essential. To enhance this, operate the devices at maximum current over capacitance. LFSR architectures build with various types of D flip flop and XOR gate circuits are analyzed. Circuit level Simulation is carried out using 130 nm technologies.

scholarly journals An Ultra-Low-Power K-Band 22.2 GHz-to-26.9 GHz Current-Reuse VCO Using Dynamic Back-Gate-Biasing Technique

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 889
Author(s):  
Xiaoying Deng ◽  
Peiqi Tan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Back Gate ◽  
Ultra Low Power ◽  
Current Reuse ◽  
K Band

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

A 260-μW Down-Conversion Demodulator for MICS-Band Receiver

2016 ◽  
Vol 26 (02) ◽  
pp. 1750027 ◽  
Author(s):  
Chia-Hung Chang ◽  
Cihun-Siyong Alex Gong ◽  
Jian-Chiun Liou ◽  
Yu-Lin Tsou ◽  
Feng-Lin Shiu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Communication Services ◽  
Ultra Low Power ◽  
Resistive Feedback ◽  
Mics Band ◽  
Down Conversion ◽  
Implant Communication

This paper showcases a low-power demodulator for medical implant communication services (MICS) applications. Complementary shunt resistive feedback, current reuse configuration, and sub-threshold LO driving techniques are proposed to achieve ultra-low power consumption. The chip has been implemented in standard CMOS process and consumes only 260-[Formula: see text]W.

scholarly journals Power Management in Low-Power MCUs for Energy IoT Applications

2020 ◽  
Vol 2020 ◽  
pp. 1-12
Author(s):  
Ling Lin ◽  
Zhong Tang ◽  
Nianxiong Tan ◽  
Xiaohui Xiao
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Management ◽  
Power Supply ◽  
Sleep Mode ◽  
Cmos Process ◽  
Power Circuit ◽  
Ultra Low Power ◽  
Power Sources ◽  
Standby Power

In this paper, we identify and address the problems of designing effective power management schemes in low-power MCU design. Firstly, this paper proposes an application-based multipower domain architecture along with a variety of working modes to effectively realize the hierarchical control of power consumption. Furthermore, devices in energy IoT (eIoT) do not always work under the main power supply. When the main power supply is unavailable, the standby power supply (usually the battery) needs to maintain the operation and save the data. In order to ensure the complete isolation between these two power sources, it is always necessary to insert a diode in both select-conduction paths, respectively. In this paper, we built a stable and smooth power switching circuit into the chip, which can effectively avoid the diode voltage loss and reduce the BoM cost. In addition, in the sleep mode, considering the relaxed output voltage range and a limited driving capability requirement, an ultra-low-power standby power circuit is proposed, which can autonomously replace the internal LDO when in sleep, further reducing the sleep power consumption under the main power supply. Fabricated in a standard 0.11 μm CMOS process, our comparative analysis demonstrates substantial reduction in power consumption from 1 μA to 0.1 μA.

scholarly journals Eight-Bit Semiflash A/D Converter

VLSI Design ◽  
2007 ◽  
Vol 2007 ◽  
pp. 1-7 ◽  
Author(s):  
D. P. Dimitrov ◽  
T. K. Vasileva
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Experimental Results ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Mixed Signal ◽  
Sample And Hold ◽  
Reduced Power Consumption ◽  
Subtraction Circuit

An 8-bit semiflash ADC is reported that uses a single array of 15 comparators for both the coarse and the fine conversion. Conversion is implemented in two steps. First, an estimate is made of the 4 most significant bits, which are then memorized in the output latch. Next, the remaining 4 bits are evaluated by the same array of comparators. The auto-zeroed comparators also perform the function of a sample-and-hold circuit. In the proposed 8-bit semiflash ADC, there are no sample-and-hold circuit, no DAC, no subtraction circuit, and no residue amplifier. As a result, a moderate conversion speed has been combined with a drastically reduced power consumption. The ADC was fabricated in a standard 0.6 μm double-poly, double-metal CMOS process. Experimental results show monotonic conversion with very low integral and differential nonlinearities. These features, combined with the ultra-low power consumption, make the proposed circuit very suitable for low-power mixed-signal applications.

An Ultra-low Power Consumption MAC Protocol Complied with IEEE 802.15.4/4e for Wireless Smart Utility Networks

2016 ◽  
Vol 136 (11) ◽  
pp. 1555-1566 ◽  
Author(s):  
Jun Fujiwara ◽  
Hiroshi Harada ◽  
Takuya Kawata ◽  
Kentaro Sakamoto ◽  
Sota Tsuchiya ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Ieee 802.15.4 ◽  
Mac Protocol ◽  
Low Power Consumption ◽  
Ultra Low Power

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

scholarly journals Ultra Low Power Consumption for Self-Oscillating Nanoelectromechanical Systems Constructed by Contacting Two Nanowires

Nano Letters ◽  
2013 ◽  
Vol 13 (4) ◽  
pp. 1451-1456 ◽  
Author(s):  
T. Barois ◽  
A. Ayari ◽  
P. Vincent ◽  
S. Perisanu ◽  
P. Poncharal ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Nanoelectromechanical Systems ◽  
Low Power Consumption ◽  
Ultra Low Power
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