Capacitive Boosted Ring Oscillators for All-Digital Phase-Locked Loops (ADPLLs)

Ring oscillator (RO)-based digital phase-locked loops (DPLLs) are very attractive for system-on-chip applications due to their tuning range, good phase noise property but suffer from compactness and power requirements. In this work, the concept of capacitive boosting as one of the key solutions which enhances the amplitude of oscillations of the RO is proposed, making it a suitable solution to the biomedical applications, specifically for medical implant communication system (MICS) band of operation ranging from 400[Formula: see text]MHz to 405[Formula: see text]MHz. With coarse and fine-tuning blocks, this digitally controlled oscillator (DCO) promises a good resolution. The coarse tuning is achieved using conventional MOS capacitors and the fine-tuning is achieved by controlling the fractional metal oxide semiconductor (MOS) capacitances. To benchmark the performance metrics of the single-stage RO in this work, simulations were performed for 680[Formula: see text]mV supply voltage in 45[Formula: see text]nm complementary metal oxide semiconductor (CMOS) technology. The output varies in the range from [Formula: see text]0.422[Formula: see text]V to [Formula: see text][Formula: see text]V, indicating about 224% amplitude enhancement. Despite process voltage temperature (PVT) variations, we can see little impact on the boosted output levels. The designed DCO operates up to a maximum frequency of 495[Formula: see text]MHz at 0.68[Formula: see text]V. The proposed RO has lesser power consumption than any conventional RO, operating at a center frequency of 402[Formula: see text]MHz, thus making it better suitable for the MICS band of applications. Phase noise of [Formula: see text][Formula: see text]dBc/Hz at an offset of 200[Formula: see text]kHz was obtained. The proposed differential DCO consumed power was 95.26[Formula: see text][Formula: see text]W. The figure of merit (FoM) for this DCO is [Formula: see text] (dBc/Hz). The area consumed by the DCO is 0.01872[Formula: see text]mm2.

A CMOS implementation of controller based all digital phase locked loop (ADPLL)

Purpose Biomedical radio frequency (RF) transceivers require miniaturized forms with long battery life and low power consumption. The medical implant communication service (MICS) band in the frequency range of 402–405 MHz is widely used for medical RF transceivers because the MICS band signals have reasonable propagation characteristics and are suited to achieve good results. The implementation of the RF front-end for medical devices has many challenges as these dictate low power consumption. In particular, phase-locked loop is one of the most critical blocks of the RF front-end. The purpose of this paper is to the design of controller-based all-digital phase-locked loop (ADPLL) in a 45 nm CMOS process. Design/methodology/approach Initially, an open-loop architecture phase frequency detector (PFD) is designed. Then based on the concept of differential buffer, a differential ring oscillator (RO) is built using capacitive boosting technique. After that, the frequency controller block is built by proper mathematical modeling that does the job of loop filter, which behaves like a phase interpolator. Frequency controller block has tuning register block, tuning word register. The tuning block is built using the Metal Oxide Semiconductor (MOS) caps. Finally, the integration of all the blocks is done and the ADPLL architecture that locks at 402 MHz is achieved. Findings The designed PFD is dead zone free that operates at 1 GHz. The differential RO oscillates at 495 MHz. The proposed ADPLL operates at 402 MHz with measured phase noise of −98.36 at 1-MHz offset. This ADPLL exhibits rms jitter of 4.626 ps with a total power consumption of 216.5 µW. Research limitations/implications A time to digital converter (TDC)-less controller-based low power ADPLL covering the MICS frequency band for biomedical applications has been designed in 45 nm/0.68 V CMOS technology. The ADPLL proposed in this draft uses differential oscillator with capacitively boosted technique which reduced the operating voltage to as low as 0.68 V. This ADPLL has a bandwidth of 20 kHz and works at reference frequency of 20 MHz consumed power of 216.5 µW, while generating an output frequency of 402 MHz. The tuning range is from 375 to 428 MHz. With the phase noise of −98.36 dbc/Hz at 1 MHz, a frequency controller block replaces the usage of TDC. Social implications The designed ADPLL will definitely pave way to greater research arena in the field of biomedical field. This ADPLL is a unique combination that combines electronics and biomedical field. The designed ADPLL is itself a broader application to biomedical field that will have a positive impact on the society. Originality/value The implementation of open-loop PFD and RO using the capacitive boosting technique is a unique combination. This is comprehended well with frequency controller block that eliminates the usage of TDC and behaves as phase interpolator. The entire design of ADPLL which suits the application of MICS band of frequency has been designed carefully to work at low power.