scholarly journals Eight-Bit Semiflash A/D Converter

VLSI Design ◽  
2007 ◽  
Vol 2007 ◽  
pp. 1-7 ◽  
Author(s):  
D. P. Dimitrov ◽  
T. K. Vasileva
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Experimental Results ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Mixed Signal ◽  
Sample And Hold ◽  
Reduced Power Consumption ◽  
Subtraction Circuit

An 8-bit semiflash ADC is reported that uses a single array of 15 comparators for both the coarse and the fine conversion. Conversion is implemented in two steps. First, an estimate is made of the 4 most significant bits, which are then memorized in the output latch. Next, the remaining 4 bits are evaluated by the same array of comparators. The auto-zeroed comparators also perform the function of a sample-and-hold circuit. In the proposed 8-bit semiflash ADC, there are no sample-and-hold circuit, no DAC, no subtraction circuit, and no residue amplifier. As a result, a moderate conversion speed has been combined with a drastically reduced power consumption. The ADC was fabricated in a standard 0.6 μm double-poly, double-metal CMOS process. Experimental results show monotonic conversion with very low integral and differential nonlinearities. These features, combined with the ultra-low power consumption, make the proposed circuit very suitable for low-power mixed-signal applications.

A 260-μW Down-Conversion Demodulator for MICS-Band Receiver

2016 ◽  
Vol 26 (02) ◽  
pp. 1750027 ◽  
Author(s):  
Chia-Hung Chang ◽  
Cihun-Siyong Alex Gong ◽  
Jian-Chiun Liou ◽  
Yu-Lin Tsou ◽  
Feng-Lin Shiu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Communication Services ◽  
Ultra Low Power ◽  
Resistive Feedback ◽  
Mics Band ◽  
Down Conversion ◽  
Implant Communication

This paper showcases a low-power demodulator for medical implant communication services (MICS) applications. Complementary shunt resistive feedback, current reuse configuration, and sub-threshold LO driving techniques are proposed to achieve ultra-low power consumption. The chip has been implemented in standard CMOS process and consumes only 260-[Formula: see text]W.

An Ultra-low Power Consumption MAC Protocol Complied with IEEE 802.15.4/4e for Wireless Smart Utility Networks

2016 ◽  
Vol 136 (11) ◽  
pp. 1555-1566 ◽  
Author(s):  
Jun Fujiwara ◽  
Hiroshi Harada ◽  
Takuya Kawata ◽  
Kentaro Sakamoto ◽  
Sota Tsuchiya ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Ieee 802.15.4 ◽  
Mac Protocol ◽  
Low Power Consumption ◽  
Ultra Low Power

scholarly journals Ultra Low Power Consumption for Self-Oscillating Nanoelectromechanical Systems Constructed by Contacting Two Nanowires

Nano Letters ◽  
2013 ◽  
Vol 13 (4) ◽  
pp. 1451-1456 ◽  
Author(s):  
T. Barois ◽  
A. Ayari ◽  
P. Vincent ◽  
S. Perisanu ◽  
P. Poncharal ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Nanoelectromechanical Systems ◽  
Low Power Consumption ◽  
Ultra Low Power

scholarly journals An Ultra-Low-Power K-Band 22.2 GHz-to-26.9 GHz Current-Reuse VCO Using Dynamic Back-Gate-Biasing Technique

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 889
Author(s):  
Xiaoying Deng ◽  
Peiqi Tan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Back Gate ◽  
Ultra Low Power ◽  
Current Reuse ◽  
K Band

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

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