scholarly journals Area-Efficient Pipelined FFT Processor for Zero-Padded Signals

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1397 ◽  
Author(s):  
Yongchul Jung ◽  
Jaechan Cho ◽  
Seongjoo Lee ◽  
Yunho Jung
Keyword(s):  
Logic Gate ◽  
Cmos Process ◽  
Path Delay ◽  
Cell Library ◽  
Fft Processor ◽  
Gate Count ◽  
Hardware Description ◽  
Stage 1 ◽  
Delay Elements ◽  
Area Efficient

This paper proposes an area-efficient fast Fourier transform (FFT) processor for zero-padded signals based on the radix-2 2 and the radix-2 3 single-path delay feedback pipeline architectures. The delay elements for aligning the data in the pipeline stage are one of the most complex units and that of stage 1 is the biggest. By exploiting the fact that the input data sequence is zero-padded and that the twiddle factor multiplication in stage 1 is trivial, the proposed FFT processor can dramatically reduce the required number of delay elements. Moreover, the 256-point FFT processors were designed using hardware description language (HDL) and were synthesized to gate-level circuits using a standard cell library for 65 nm CMOS process. The proposed architecture results in a logic gate count of 40,396, which can be efficient and suitable for zero-padded FFT processors.

Performance Analysis of an Area Efficient and Low Power MOD-R2MDC FFT for MIMO OFDM

2014 ◽  
Vol 573 ◽  
pp. 176-180
Author(s):  
G. Kavitha ◽  
B. Kirthiga ◽  
N. Kirubanandasarathy
Keyword(s):  
Low Power ◽  
Orthogonal Frequency Division Multiplexing ◽  
Ofdm System ◽  
Description Language ◽  
Fft Processor ◽  
Synthesis Tool ◽  
Mimo Ofdm ◽  
Hardware Description ◽  
Fft Algorithms ◽  
Area Efficient

In this paper, an area-efficient low power fast fourier transform (FFT) processor is proposed for multi input multi output-orthogonal frequency division multiplexing (MIMO-OFDM) in wireless communication system. It consists of a modified architecture of radix-2 algorithm which is described as modified radix-2 multipath delay commutation (MOD-R2MDC). The OFDM receiver with modified R2MDC (MOD-R2MDC) FFT was designed by Hardware Description Language (HDL) coding The Xilinx ISE Design Suite 10.1 is used as a synthesis tool for getting the power and area. The Model-Sim 6.3c is used for simulation. Also the existing OFDM system has been tested with these FFT algorithms and their performances were analyzed with respect to occupancy area in FPGA and power consumption. A low-power and area efficient architecture enables the real-time operations of MIMO OFDM system.

DESIGN OF AN AREA-EFFICIENT HIGH-THROUGHPUT SHIFT-BASED LDPC DECODER

2013 ◽  
Vol 22 (06) ◽  
pp. 1350039 ◽  
Author(s):  
Yun-Ching Tang ◽  
Hong-Ren Wang ◽  
Hongchin Lin ◽  
Jun-Zhe Huang
Keyword(s):  
High Throughput ◽  
Supply Voltage ◽  
Critical Path ◽  
Cmos Process ◽  
Path Delay ◽  
Clock Frequency ◽  
Storage Unit ◽  
Ldpc Decoder ◽  
Routing Congestion ◽  
Area Efficient

An area-efficient high-throughput shift-based LDPC decoder architecture is proposed. The specially designed (512, 1,024) parity-check matrix is effective for partial parallel decoding by the min-sum algorithm (MSA). To increase throughput during decoding, two data frames are fed into the decoder to minimize idle time of the check node unit (CNU) and the variable node unit (VNU). Thus, the throughput is increased to almost two-fold. Unlike the conventional architecture, the message storage unit contains shift registers instead of de-multiplexers and registers. Therefore, hardware costs are reduced. Routing congestion and critical path delay are also reduced, which increases energy efficiency. An implementation of the proposed decoder using TSMC 0.18 μm CMOS process achieves a decoding throughput of 1.725 Gbps, at a clock frequency of 56 MHz, a supply voltage of 1.8 V, and a core area of 5.18 mm2. The normalized area is smaller and the throughput per normalized power consumption is higher than those reported using the conventional architectures.

scholarly journals Area-efficient mixed-radix variable-length FFT processor

2017 ◽  
Vol 14 (10) ◽  
pp. 20170232-20170232 ◽  
Author(s):  
Chen Yang ◽  
Chunpeng Wei ◽  
Yizhuang Xie ◽  
He Chen ◽  
Cuimei Ma
Keyword(s):  
Variable Length ◽  
Fft Processor ◽  
Area Efficient

scholarly journals A Novel Architecture of Radix-3 Singlepath Delay Feedback (R3SDF) FFT Using MCSLA

2018 ◽  
Vol 10 (1) ◽  
pp. 37
Author(s):  
Periyarselvam K ◽  
Saravanakumar G ◽  
Anand M
Keyword(s):  
Power Consumption ◽  
Orthogonal Frequency Division Multiplexing ◽  
Digital Signal ◽  
Path Delay ◽  
Hardware Complexity ◽  
Large Power ◽  
Fft Processor ◽  
Novel Design ◽  
Multiplexing Systems ◽  
Single Path

Fast Fourier transform (FFT) is widely used in digital signal processing and telecommunications, particularly in orthogonal frequency division multiplexing systems, to overcome the problems associated with orthogonal subcarriers. A new algorithm of radix-3 FFT has been introduced in this work. The DFT of length N can be realized from three DFT sequences; each of length N/3.Radix-3 algorithm reduces the number of multiplications required for realizing DFT.A novel design of Radix-3pipelined Single path Delay Feedback (R3SDF) FFT using MCSLA has been proposed in this paper. First, the pipelined radix-3 SDF FFT method has been designed. It has less area and large power consumption and delay. In order to overcome these problems, modified carry select adder structure is used to perform the adder operation for reducing the power consumption and delay. Finally, the MCSLA is integrated into radix-3 SDF FFT processor. The hardware complexity and execution time for implementing radix-3 FFT algorithm can be reduced than other FFTs.

scholarly journals Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique

2020 ◽  
Vol 9 (12) ◽  
pp. 323-328
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Circuit Simulation ◽  
Full Adder ◽  
Cmos Process ◽  
Path Delay ◽  
Process Technology ◽  
Xnor Gate

VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR/XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR/XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model.

scholarly journals Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library

VLSI Design ◽  
2000 ◽  
Vol 11 (4) ◽  
pp. 331-338 ◽  
Author(s):  
Chua-Chin Wang ◽  
Chenn-Jung Huang ◽  
I-Yen Chang
Keyword(s):  
High Speed ◽  
Hardware Description Language ◽  
Verilog Hdl ◽  
Description Language ◽  
Throughput Rate ◽  
Cell Library ◽  
Conversion Algorithm ◽  
Hardware Description ◽  
Simulation Results

A high speed 64b/32b integer divider employing digit-recurrence division method and the on-the-fly conversion algorithm, wherein a fast normalizer is included, which is used as the pre-processor of the proposed integer divider. For the sake of enhancing throughput rate, the proposed divider uses a mixed radix-8/4/2 division instead of the traditional radix-2 division. On-the-fly remainder adjustment is also realized in the converter module of the divider. The entire design is written in Verilog HDL (hardware description language) employing COMPASS 0.6 μm 1P3M cell library (V3.0), and then synthesized by SYNOPSYS. The simulation results indicate that our design is a better option than the existing long divider designs.

A New Automatic Readout Circuit for a Gas Sensor With Organic Vertical Nano-Junctions

2016 ◽  
Author(s):  
Hung-Che Chen ◽  
Yung-Hua Kao ◽  
Paul C.-P. Chao ◽  
Chin-Long Wey
Keyword(s):  
Gas Sensor ◽  
Low Cost ◽  
Logic Gate ◽  
Control Unit ◽  
Ammonia Concentration ◽  
Added Value ◽  
Cmos Process ◽  
Readout Circuit ◽  
Readout System ◽  
Operational Errors

The design of the proposed readout circuit provides benefits of detection speed, portability, low-cost and less human operational errors compared with the measurement by traditional instruments. Thus the added value is brought for biosensors and applied in home care. A novel readout circuit for a gas sensor based on an organic diode with vertical nano-junctions (VNJ) is proposed in this study. There are seven parts included in the readout system. First part is a preamplifier, second part is a peak-detect-and-hold circuit, third part is a divider, fourth part is the saturation detector, fifth part is the auto-reset circuit, sixth part is a logic gate and a buffer, seventh part is a micro-processor control unit (MCU). STM32 is the CPU of proposed MCU by ALIENTEK. The ADC of MCU is used to transform the output data of readout circuit. The designed circuit is accomplished by Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 μm 2P4M 3.3 V mixed signal CMOS process, the area of chip is 0.74×0.75 mm2. Finally, the differences between experimental results with post-simulation results in 10 ppb ∼ 3 ppm of ammonia, the differences are within 7.24%. The sensing system is able to detect minimum ammonia concentration of 10 ppb, while the maximum one reaches around 3 ppm.

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