scholarly journals A Novel Offset and Finite-Gain Compensated Switched-Capacitor Amplifier with Input Correlated Level Shifting

Electronics ◽  
2019 ◽  
Vol 8 (9) ◽  
pp. 986
Author(s):  
Yan Chen ◽  
Yousheng Chen ◽  
Yan Guo ◽  
Chunxia Li
Keyword(s):  
Cmos Technology ◽  
Double Sampling ◽  
Switched Capacitor ◽  
Dc Offset ◽  
Op Amp ◽  
Correlated Double Sampling ◽  
Gain Error ◽  
Dc Gain ◽  
Finite Gain ◽  
Correlated Level Shifting

A novel offset and finite-gain compensated differential switched-capacitor(SC) amplifier is presented. Incorporating the correlated double sampling (CDS) technique and input correlated level shifting (CLS) technique together, the DC offset and DC gain error of SC amplifier are further reduced by a factor of op-amp DC gain compared with the conventional offset and finite-gain compensated SC amplifier. The effectiveness of the new scheme has been analyzed and verified by extensive simulations. An SC amplifier with the proposed scheme is designed in 130 nm CMOS technology. Simulated results show that with an op-amp having a low DC gain of 30 dB and an input offset of 10 mV, the proposed SC amplifier achieves an output offset and DC-gain error of 154 µV and 0.05%, respectively, which are significantly improved compared with 1.155 mV and 0.42% achieved in the conventional SC amplifier.

A New Sub-1 Volt 17ppm/°C Offset-Insensitive Resistorless Switched-Capacitor Bandgap Voltage Reference

2020 ◽  
pp. 2150029
Author(s):  
Emad Ebrahimi ◽  
Maliheh Arabnasery
Keyword(s):  
Process Variations ◽  
Voltage Divider ◽  
Cmos Technology ◽  
Reference Voltage ◽  
Cmos Process ◽  
Switched Capacitor ◽  
Voltage Reference ◽  
Op Amp ◽  
Offset Voltage ◽  
Bandgap Voltage Reference

A new PVT compensated voltage reference is presented by using switched-capacitor (S.C.) technique. In the proposed bandgap voltage reference (BGR), a p–n junction is biased with different currents during two different phases and required PTAT and CTAT voltages generated and held by two capacitors. Using a capacitive voltage divider, the PTAT voltage is weighted such that the sub-1V bandgap voltage is achievable. In order to cancel the effect of op-amp offset and to relax the design of op-amp, the offset voltage of the op-amp is sampled by a capacitor during a specified phase and inversely is added to the final bandgap voltage in next phase. The analysis of the proposed S.C. BGR is supplemented by simulation of a 0.5-V BGR with 28[Formula: see text][Formula: see text][Formula: see text]W power consumption in a standard 0.18[Formula: see text][Formula: see text][Formula: see text]m CMOS technology. Simulation results show that the average temperature coefficient of the S.C. BGR is 17[Formula: see text]ppm/∘C and it is robust against the process variations. Applying an arbitrary 100-mV op-amp offset results in a lower than 1.1[Formula: see text]mV deviation in generated reference voltage. Due to the better matching of MIM capacitors in CMOS process (rather than resistors used in conventional BGR) the proposed S.C. bandgap provides good accuracy without any post trimming. Monte–Carlo analysis shows that [Formula: see text]/[Formula: see text] of the generated reference voltage is as low as 0.7%. The sensitivity of the proposed BGR to supply variation is also less than 1%/V.

Readout Circuit for Uncooled Pyroelectric IRFPA

2011 ◽  
Vol 84-85 ◽  
pp. 284-288
Author(s):  
Fei Bao Lu ◽  
Guo Lin Lu ◽  
You Shu Huang ◽  
Xiang Hui Yuan
Keyword(s):  
Power Dissipation ◽  
Infrared Detector ◽  
Cmos Technology ◽  
Shift Register ◽  
Double Sampling ◽  
Readout Circuit ◽  
Thermal Images ◽  
Correlated Double Sampling ◽  
Circuit Configuration

A 320×240 readout circuit (ROIC) for the uncooled pyroelectric infrared detector was fabricated in the double-poly-double-metal (DPDM) N-well CMOS technology. Composed of X- and Y-shift register, column amplifier and correlated double sampling (CDS) circuit, the readout circuit integrated signal from the detector for frame time. It has the pitch of 50um and power dissipation of less than 50 mW. The circuit configuration, operation and testing result are described. Testing result indicates that the designed circuit meets with the requirement. Thermal images were obtained by the hybrid-integrated sensing array.

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