programmable gain amplifier
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2020 ◽  
Vol 10 (5) ◽  
pp. 558-576
Author(s):  
T.A. Anusudha ◽  
S.S. Reka ◽  
S.R.S. Prabaharan

The emergence of memristor offers new avenues to look at several potential applications ranging from non-volatile memories to neuromorphic system. A typical sign of the physical memristor device is Pinched Hysteresis Loop. In the aspect of accomplishing this loop with high accuracy, several memristor models have been evolved in the past. Moreover, various mathematical window functions have been developed from the researchers to throw more insight into the memristor model with the accordance of enhancing the degree of nonlinearity, resolving boundary effect and boundary lock. This review portrays a brief description of explored memristor models and window functions. With this, a comprehensive analysis is made to depict the advantages and disadvantages in a more explicit manner. Furthermore, this work exhibits the prevailing properties of memristor and the different types of switching mechanisms. Here, the future perspective of the memristive technology is also explored very well as the memristor has become an innovative candidate in the memory technology over the semiconductor. Memristor-based potential applications such as a fine resolution programmable gain amplifier, synapse, and logic gate are also explained briefly.


2020 ◽  
Vol 15 (1) ◽  
pp. 1-9
Author(s):  
Isaías De Sousa Barbosa Júnior ◽  
Raimundo Carlos Silverio Freire ◽  
Edelson Da Silva Procopio Venuto

Programmable Gain Amplifiers (PGA's) are circuits capable of conveniently changing their gain to address various levels of amplification. Knowing this, the topology proposed in this work takes a source degenerated first stage, a common-source with resistive load second stage, and a gm boosting circuit interface to realize a PGA that has low power consumption and low area. The design developed was able to achieve a maximum power dissipation of 103.1 uW, a minimum bandwidth of 5.59 MHz, a maximum noise of 32.01 nV/sqrt(Hz), and a gain range of 2.31 - 19.84 dB. Each differential output of the circuit is loaded with 700 fF, which is the estimated load for the hypothetical following block, the Analog-to-Digital Converter (ADC). Furthermore, the supply voltage of the circuit is 1 V and the design was undertaken on Global Foundrie's 130 nm technology. The phase margin of the core circuit is no greater than 100.3˚  and no less than 49˚  . The circuit which design is described in this work is intended to be within the receiver (RX) sub-domain of a Bluetooth Low-Energy (BLE) system, which finds applications on the IoT and healthcare industries, for instance.


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