scholarly journals Development of an Advanced TDDB Analysis Model for Temperature Dependency

Electronics ◽  
2019 ◽  
Vol 8 (9) ◽  
pp. 942
Author(s):  
Kiron Park ◽  
Keonho Park ◽  
Sujin Im ◽  
SeungEui Hong ◽  
Kwonjoo Son ◽  
...  
Keyword(s):  
Dielectric Layer ◽  
Dielectric Breakdown ◽  
Failure Detection ◽  
Accelerated Life Test ◽  
Hole Injection ◽  
Degradation Mechanisms ◽  
Analysis Model ◽  
Time Dependent Dielectric Breakdown ◽  
Proposed Model ◽  
Anode Hole Injection

This paper proposes a hybrid model to describe the temperature dependence of the time-dependent dielectric breakdown (TDDB) phenomenon. TDDB can be expressed in terms of two well-known representative degradation mechanisms: The thermo-chemical (TC) mechanism and the anode hole injection (AHI) mechanism. A single model does not account for the measured lifetime, due to TDDB under different temperature conditions. Hence, in the proposed model, two different degradation mechanisms are considered simultaneously in an appropriate manner to describe the trap generation in the dielectric layer. The proposed model can be used to simulate the generation of the percolation path in a dielectric layer, and it is in agreement with the measured lifetime because of TDDB at different temperatures. Therefore, the proposed model can be used to predict guarantee time or initial failure detection, using the accelerated life test for industrial purposes.

Assessment of Reliability of cap layers used in Cu-Black DiamondTM Interconnects

2003 ◽  
Vol 766 ◽  
Author(s):  
Ahila Krishnamoorthy ◽  
N.Y. Huang ◽  
Shu-Yunn Chong
Keyword(s):  
Dielectric Layer ◽  
Dielectric Breakdown ◽  
Copper Ions ◽  
Dielectric Strength ◽  
Time Dependent ◽  
Breakdown Field ◽  
Field Range ◽  
Time Dependent Dielectric Breakdown ◽  
Voltage Ramp ◽  
Low K

AbstractBlack DiamondTM. (BD) is one of the primary candidates for use in copper-low k integration. Although BD is SiO2 based, it is vastly different from oxide in terms of dielectric strength and reliability. One of the main reliability concerns is the drift of copper ions under electric field to the surrounding dielectric layer and this is evaluated by voltage ramp (V-ramp) and time dependent dielectric breakdown (TDDB). Metal 1 and Metal 2 intralevel comb structures with different metal widths and spaces were chosen for dielectric breakdown studies. Breakdown field of individual test structures were obtained from V-ramp tests in the temperature range of 30 to 150°C. TDDB was performed in the field range 0.5 – 2 MV/cm. From the leakage between combs at the same level (either metal 1 or metal 2) Cu drift through SiC/BD or SiN/BD interface was characterized. It was found that Cu/barrier and barrier/low k interfaces functioned as easy paths for copper drift thereby shorting the lines. Cu/SiC was found to provide a better interface than Cu/SiN.

PHYSICS AND CHEMISTRY OF INTRINSIC TIME-DEPENDENT DIELECTRIC BREAKDOWN IN SiO2 DIELECTRICS

2001 ◽  
Vol 11 (03) ◽  
pp. 751-787 ◽  
Author(s):  
J. W. McPHERSON
Keyword(s):  
Elevated Temperatures ◽  
Dielectric Breakdown ◽  
Oxide Thickness ◽  
Time Dependent ◽  
Hole Injection ◽  
Time Dependent Dielectric Breakdown ◽  
Bond Breakage ◽  
Bond Strengths ◽  
Breakage Mechanism ◽  
Molecular Bonding

A molecular physics-based complementary model, which includes both field-induced and current-induced degradation mechanisms, is used to help resolve the E versus 1/E time-dependent dielectric breakdown (TDDB) model controversy that has existed for many years. The Complementary Model indicates either the E or 1/E–TDDB model can be valid for certain specified field, temperature, and molecular bonding-energy ranges. For bond strengths <3 eV, the bond breakage rate is generally dominated by field-enhanced thermal processes at lower fields and elevated temperatures where the E-model is valid. At higher fields, lower temperatures and higher bond strengths the bond breakage mechanism must be hole-catalyzed and the TDDB physics is described well by the 1/E-model. Neither the E-model nor 1/E-model works well for oxide thickness below tox < 4 nm where direct tunneling effects dominate in these hyper-thin films. The increase in DT leakage leads to more hole injection and trapping in the SiO 2. This enhanced dielectric degradation rate with tox reduction can be easily incorporated into the Complementary Model where hole capture serves to catalyze Si–O bond breakage.

Passivation by N Implantation of the SiO2/SiC Acceptor Interface States: Impact on the Oxide Hole Traps and the Gate Oxide Reliability

2010 ◽  
Vol 1246 ◽  
Author(s):  
Antonella Poggi ◽  
Francesco Moscatelli ◽  
Sandro Solmi ◽  
Roberta Nipoti
Keyword(s):  
Dielectric Breakdown ◽  
Shallow Donor ◽  
Hole Injection ◽  
Light Illumination ◽  
Oxide Interface ◽  
Mos Capacitors ◽  
Time Dependent Dielectric Breakdown ◽  
Equivalent Time ◽  
Static Capacitance ◽  
White Light Illumination

AbstractThis study compares p-MOS capacitors fabricated on N+ implanted and on virgin 4H-SiC. The former sample have N at the SiO2/SiC interface, the latter have not. To investigate the presence of deep and shallow hole traps at the SiO2/SiC interface, high frequency and quasi-static capacitance voltage measurements under dark have been compared for bias sweeping from accumulation to depletion and from depletion to accumulation, the latter after white light illumination. The presence of N has an effect on the density of the shallow donor like traps but none effect on the deep ones. The positive charge trapped in the oxide and/or at the oxide interface after equivalent tunneling hole injection have been compared and are equivalent. Time dependent dielectric breakdown tests have been compared too. The oxide grown on N+implanted SiC broken at lower electric field.

A Novel Integrated Reliability Test System for BEOL TDDB Study

2012 ◽  
Author(s):  
Jifeng Chen ◽  
Peilin Song ◽  
Thomas M. Shaw ◽  
Franco Stellari ◽  
Lynne Gignac ◽  
...  
Keyword(s):  
Preliminary Analysis ◽  
Dielectric Breakdown ◽  
Test System ◽  
Accurate Information ◽  
Reliability Test ◽  
Electrical Measurements ◽  
Time Dependent Dielectric Breakdown ◽  
Microscopy Images ◽  
Insight Into

Abstract In this paper, we propose a new methodology and test system to enable the early detection and precise localization of Time-Dependent-Dielectric-Breakdown (TDDB) occurrence in Back-End-of-Line (BEOL) interconnection. The methodology is implemented as a novel Integrated Reliability Test System (IRTS). In particular, through our methodology and test system, we can easily synchronize electrical measurements and emission microscopy images to gather more accurate information and thereby gain insight into the nature of the defects and their relationship to chip manufacturing steps and materials, so that we can ultimately better engineer these steps for higher reliable systems. The details of our IRTS will be presented along with a case study and preliminary analysis results.

Noise Analysis of the Leakage Current in Time-Dependent Dielectric Breakdown in a GaN SLCFET

2021 ◽  
Vol 68 (5) ◽  
pp. 2220-2225
Author(s):  
Stefano Dalcanale ◽  
Michael J. Uren ◽  
Josephine Chang ◽  
Ken Nagamatsu ◽  
Justin A. Parke ◽  
...  
Keyword(s):  
Leakage Current ◽  
Dielectric Breakdown ◽  
Noise Analysis ◽  
Time Dependent ◽  
Time Dependent Dielectric Breakdown

Reliability of Metal Gate / High-k devices and its impact on CMOS technology scaling

MRS Advances ◽  
2017 ◽  
Vol 2 (52) ◽  
pp. 2973-2982 ◽  
Author(s):  
Andreas Kerber
Keyword(s):  
Dielectric Breakdown ◽  
Cmos Technology ◽  
Gate Stack ◽  
Leakage Currents ◽  
Technology Scaling ◽  
Device Scaling ◽  
Novel Device ◽  
Time Dependent Dielectric Breakdown ◽  
Bias Temperature Instability ◽  
High K

ABSTRACTMG/HK was introduced into CMOS technology and enabled scaling beyond the 45/32nm technology node. The change in gate stack from poly-Si/SiON to MG/HK introduced new reliability challenges like the positive bias temperature instability (PBTI) and stress induced leakage currents (SILC) in nFET devices which prompted thorough investigation to provide fundamental understanding of these degradation mechanisms and are nowadays well understood. The shift to a dual-layer gate stack also had a profound impact on the time dependent dielectric breakdown (TDDB) introducing a strong polarity dependence in the model parameter. As device scaling continues, stochastic modeling of variability, both at time zero and post stress due to BTI, becomes critical especially for SRAM circuit aging. As we migrate towards novel device architectures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices, impact of self-heating needs to be accounted for in reliability testing.In this paper we summarize the fundamentals of MG/HK reliability and discuss the reliability and characterization challenges related to the scaling of future CMOS technologies.

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