scholarly journals A Semi-Floating Gate Memory with Tensile Stress for Enhanced Performance

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 414
Author(s):  
Yuan ◽  
Jiang ◽  
Sun ◽  
Chen ◽  
Zhu ◽  
...  
Keyword(s):  
Tensile Stress ◽  
Random Access ◽  
Drain Current ◽  
Floating Gate ◽  
Retention Performance ◽  
Operation Speed ◽  
Floating Gate Transistor ◽  
Floating Gate Memory ◽  
Etch Stop ◽  
Etch Stop Layer

With the continuous scaling down of devices, traditional one-transistor one-capacitor dynamic random access memory (1T-1C DRAM) has encountered great challenges originated from the large-volume capacitor and high leakage current. A semi-floating gate transistor has been proposed as a capacitor-less memory with ultrafast speed and silicon-compatible technology. In this work, a U-shaped semi-floating gate memory with strain technology has been demonstrated through TCAD simulation. Ultra-high operation speed on a timescale of 5 ns at low operation voltages (≤ 2.0 V) has been obtained. And the tensile stress induced in its channel region by using contact etch stop layer (Si3N4 capper layer) was found to significantly improve the drain current by 12.07%. Furthermore, this device demonstrated a favorable retention performance with a retention time over 1 s, and its immunity to disturbance from bit-line has also been investigated that could maintain data under the continuous worst writing disturbance operation over 10 ms.

Performance of Direct Tunneling Floating Gate Memory with Medium-κ Dielectrics for Embedded-Random-Access Memory Applications

2006 ◽  
Vol 45 (4B) ◽  
pp. 3170-3175
Author(s):  
Bogdan Govoreanu ◽  
Robin Degraeve ◽  
Thomas Kauerauf ◽  
Wim Magnus ◽  
Dirk Wellekens ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Floating Gate ◽  
Access Memory ◽  
Direct Tunneling ◽  
Floating Gate Memory ◽  
Memory Applications

scholarly journals A Semi-Floating Gate Memory Based on SOI Substrate by TCAD Simulation

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1198
Author(s):  
Han Li ◽  
Chen Wang ◽  
Lin Chen ◽  
Hao Zhu ◽  
Qingqing Sun
Keyword(s):  
Computer Aided Design ◽  
Random Access ◽  
Floating Gate ◽  
Silicon On Insulator ◽  
Semiconductor Electronic ◽  
Floating Gate Memory ◽  
Retention Characteristics ◽  
Tcad Simulation ◽  
Aided Design ◽  
Physical Challenges

Over the past decade, the dimensional scaling of semiconductor electronic devices has been facing fundamental and physical challenges, and there is currently an urgent need to increase the ability of dynamic random-access memory (DRAM). A semi-floating gate (SFG) transistor has been proposed as a capacitor-less memory with faster speed and higher density as compared with the conventional one-transistor one-capacitor (1T1C) DRAM technology. The integration of SFG-based memory on the silicon-on-insulator (SOI) substrate has been demonstrated in this work by using the Sentaurus Technology Computer-Aided Design (TCAD) simulation. An enhancement in retention characteristics, anti-disturbance ability, and fast writing capability, have been illustrated. The device exhibits a low operation voltage, a large threshold voltage window of ~3 V, and an ultra-fast writing of 4 ns. In addition, the SOI-based memory has shown a much-improved anti-irradiation capability compared to the devices based on bulk silicon, which makes it much more attractive in broader applications.

A Semi-Floating Gate Transistor for Low-Voltage Ultrafast Memory and Sensing Operation

Science ◽  
2013 ◽  
Vol 341 (6146) ◽  
pp. 640-643 ◽  
Author(s):  
Peng-Fei Wang ◽  
Xi Lin ◽  
Lei Liu ◽  
Qing-Qing Sun ◽  
Peng Zhou ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Voltage ◽  
Drain Current ◽  
Floating Gate ◽  
Image Sensing ◽  
Floating Gate Transistor ◽  
Physical Limitations ◽  
Effect Transistor ◽  
And Performance

As the semiconductor devices of integrated circuits approach the physical limitations of scaling, alternative transistor and memory designs are needed to achieve improvements in speed, density, and power consumption. We report on a transistor that uses an embedded tunneling field-effect transistor for charging and discharging the semi-floating gate. This transistor operates at low voltages (≤2.0 volts), with a large threshold voltage window of 3.1 volts, and can achieve ultra–high-speed writing operations (on time scales of ~1 nanosecond). A linear dependence of drain current on light intensity was observed when the transistor was exposed to light, so possible applications include image sensing with high density and performance.

Characteristics of the SiN Uniaxial Strained NMOSFET with Channel Fluorine Implantation

2011 ◽  
Vol 383-390 ◽  
pp. 3178-3182
Author(s):  
Yung Yu Chen ◽  
Chih Ren Hsieh ◽  
Fang Yu Chiu
Keyword(s):  
Field Effect Transistor ◽  
Drain Current ◽  
Oxide Semiconductor ◽  
Uniaxial Tensile ◽  
Hot Electron ◽  
Threshold Voltage Shift ◽  
Voltage Stress ◽  
Etch Stop ◽  
Etch Stop Layer ◽  
Effect Transistor

Channel fluorine implantation (CFI) has been successfully integrated with silicon nitride contact etch stop layer (SiN CESL) to further improve the channel hot electron stress (CHES) and constant voltage stress (CVS) reliability of n-channel metal-oxide-semiconductor field-effect-transistor with HfO2/SiON gate stack. Although the improvement of transconductance, drain current and subthreshold swing due to the fluorine passivation is screened out by the effect of uniaxial tensile strain, the result clearly demonstrates that integrating the CFI process in the SiN CESL-strained device can further suppress the CHES- and CVS-induced threshold voltage shift.

Significantly improving sub-90nm CMOSFET performances with notch-gate enhanced high tensile-stress contact etch stop layer

2008 ◽  
Vol 48 (11-12) ◽  
pp. 1791-1794 ◽  
Author(s):  
Chia-Wei Hsu ◽  
Yean-Kuen Fang ◽  
Wen-Kuan Yeh ◽  
Chien-Ting Lin
Keyword(s):  
Tensile Stress ◽  
Etch Stop ◽  
Etch Stop Layer

Floating Gate Memory Based on Ferritin Nanodots with High-kGate Dielectrics

2009 ◽  
Vol 48 (4) ◽  
pp. 04C153 ◽  
Author(s):  
Kosuke Ohara ◽  
Yukiharu Uraoka ◽  
Takashi Fuyuki ◽  
Ichiro Yamashita ◽  
Toshitake Yaegashi ◽  
...  
Keyword(s):  
Floating Gate ◽  
Floating Gate Memory

scholarly journals Single-Poly Floating-Gate Memory Cell Options for Analog Neural Networks

2021 ◽  
pp. 108062
Author(s):  
Maksym Paliy ◽  
Tommaso Rizzo ◽  
Piero Ruiu ◽  
Sebastiano Strangio ◽  
Giuseppe Iannaccone
Keyword(s):  
Neural Networks ◽  
Memory Cell ◽  
Floating Gate ◽  
Floating Gate Memory ◽  
Analog Neural Networks

scholarly journals Using Floating-Gate Memory to Train Ideal Accuracy Neural Networks

2019 ◽  
Vol 5 (1) ◽  
pp. 52-57 ◽  
Author(s):  
Sapan Agarwal ◽  
Diana Garland ◽  
John Niroula ◽  
Robin B. Jacobs-Gedrim ◽  
Alex Hsia ◽  
...  
Keyword(s):  
Neural Networks ◽  
Floating Gate ◽  
Floating Gate Memory
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