scholarly journals Analysis and Simulations of Hybrid Memory Scheme Based on Memristors

Electronics ◽  
2018 ◽  
Vol 7 (11) ◽  
pp. 289 ◽  
Author(s):  
Valeri Mladenov
Keyword(s):  
Operating Mode ◽  
Window Function ◽  
Oxide Semiconductor ◽  
Applied Model ◽  
Drift Model ◽  
Window Functions ◽  
Current Voltage ◽  
Memory Schemes ◽  
Memory Scheme ◽  
Switching Mode

The investigation of new memory schemes is significant for future generations of electronic devices. The purpose of this research is to present a detailed analysis of the processes in the memory elements of a memory section with memristors and isolating Metal Oxide Semiconductor (MOS) transistors. For the present analysis, a modified window function previously proposed by the author in another memristor model is used. The applied model is based on physical nonlinear current-voltage and state-voltage characteristics. It is suitable for illustration of the processes in the memristors for both writing and reading procedures. The memory scheme is simulated using a nonlinear drift model with an improved window function. The used model was previously adjusted according to the reference Pickett model. The memory circuit is analyzed for writing and reading information procedures. The memristor current-voltage relationship is compared to physical experimental characteristics and to results acquired by the use of basic window functions. A satisfactory coincidence between the corresponding results is established. For the used logical signals, the memory elements operate in a state near to hard-switching mode. It is confirmed that the memristor model with a modified window function applied here is suitable for investigating complex memristor circuits for a general operating mode.

scholarly journals Continuous window functions for NFFT

2021 ◽  
Vol 47 (4) ◽  
Author(s):  
Daniel Potts ◽  
Manfred Tasche
Keyword(s):  
Fourier Transform ◽  
Shape Parameter ◽  
Optimal Choice ◽  
Approximate Algorithm ◽  
Window Function ◽  
Truncation Parameter ◽  
Error Constant ◽  
Window Functions ◽  
Nonequispaced Fast Fourier Transform ◽  
Error Behavior

AbstractIn this paper, we study the error behavior of the nonequispaced fast Fourier transform (NFFT). This approximate algorithm is mainly based on the convenient choice of a compactly supported window function. Here, we consider the continuous Kaiser–Bessel, continuous exp-type, sinh-type, and continuous cosh-type window functions with the same support and same shape parameter. We present novel explicit error estimates for NFFT with such a window function and derive rules for the optimal choice of the parameters involved in NFFT. The error constant of a window function depends mainly on the oversampling factor and the truncation parameter. For the considered continuous window functions, the error constants have an exponential decay with respect to the truncation parameter.

scholarly journals Study and Assessment of Defect and Trap Effects on the Current Capabilities of a 4H-SiC-Based Power MOSFET

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 735
Author(s):  
Fortunato Pezzimenti ◽  
Hichem Bencherif ◽  
Giuseppe De Martino ◽  
Lakhdar Dehimi ◽  
Riccardo Carotenuto ◽  
...  
Keyword(s):  
Drain Current ◽  
Oxide Semiconductor ◽  
Temperature Dependent ◽  
Channel Mobility ◽  
Blocking Voltage ◽  
Current Voltage ◽  
Wide Range ◽  
Temperature Ranges ◽  
Joint Contribution ◽  
State Resistance

A numerical simulation study accounting for trap and defect effects on the current-voltage characteristics of a 4H-SiC-based power metal-oxide-semiconductor field effect transistor (MOSFET) is performed in a wide range of temperatures and bias conditions. In particular, the most penalizing native defects in the starting substrate (i.e., EH6/7 and Z1/2) as well as the fixed oxide trap concentration and the density of states (DoS) at the 4H-SiC/SiO2 interface are carefully taken into account. The temperature-dependent physics of the interface traps are considered in detail. Scattering phenomena related to the joint contribution of defects and traps shift the MOSFET threshold voltage, reduce the channel mobility, and penalize the device current capabilities. However, while the MOSFET on-state resistance (RON) tends to increase with scattering centers, the sensitivity of the drain current to the temperature decreases especially when the device is operating at a high gate voltage (VGS). Assuming the temperature ranges from 300 K to 573 K, RON is about 2.5 MΩ·µm2 for VGS > 16 V with a percentage variation ΔRON lower than 20%. The device is rated to perform a blocking voltage of 650 V.

scholarly journals Genetic Algorithms with Memory- and Elitism-Based Immigrants in Dynamic Environments

2008 ◽  
Vol 16 (3) ◽  
pp. 385-416 ◽  
Author(s):  
Shengxiang Yang
Keyword(s):  
Genetic Algorithms ◽  
Optimization Problems ◽  
Dynamic Environments ◽  
Population Diversity ◽  
Dynamic Problems ◽  
Dynamic Optimization Problems ◽  
Hybrid Memory ◽  
Memory Schemes ◽  
Memory Scheme ◽  
With Memory

In recent years the genetic algorithm community has shown a growing interest in studying dynamic optimization problems. Several approaches have been devised. The random immigrants and memory schemes are two major ones. The random immigrants scheme addresses dynamic environments by maintaining the population diversity while the memory scheme aims to adapt genetic algorithms quickly to new environments by reusing historical information. This paper investigates a hybrid memory and random immigrants scheme, called memory-based immigrants, and a hybrid elitism and random immigrants scheme, called elitism-based immigrants, for genetic algorithms in dynamic environments. In these schemes, the best individual from memory or the elite from the previous generation is retrieved as the base to create immigrants into the population by mutation. This way, not only can diversity be maintained but it is done more efficiently to adapt genetic algorithms to the current environment. Based on a series of systematically constructed dynamic problems, experiments are carried out to compare genetic algorithms with the memory-based and elitism-based immigrants schemes against genetic algorithms with traditional memory and random immigrants schemes and a hybrid memory and multi-population scheme. The sensitivity analysis regarding some key parameters is also carried out. Experimental results show that the memory-based and elitism-based immigrants schemes efficiently improve the performance of genetic algorithms in dynamic environments.

scholarly journals Effects of top electrode material in hafnium-oxide-based memristive systems on highly-doped Si

2020 ◽  
Vol 10 (1) ◽  
Author(s):  
Sueda Saylan ◽  
Haila M. Aldosari ◽  
Khaled Humood ◽  
Maguy Abi Jaoude ◽  
Florent Ravaux ◽  
...  
Keyword(s):  
Resistive Switching ◽  
Hafnium Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Differential Resistance ◽  
Oxide Semiconductor ◽  
Bipolar Resistive Switching ◽  
Current Voltage ◽  
Device Structures ◽  
Memristive Systems ◽  
P Type

Abstract This work provides useful insights into the development of HfO2-based memristive systems with a p-type silicon bottom electrode that are compatible with the complementary metal–oxide–semiconductor technology. The results obtained reveal the importance of the top electrode selection to achieve unique device characteristics. The Ag/HfO2/Si devices have exhibited a larger memory window and self-compliance characteristics. On the other hand, the Au/HfO2/Si devices have displayed substantial cycle-to-cycle variation in the ON-state conductance. These device characteristics can be used as an indicator for the design of resistive-switching devices in various scenes such as, memory, security, and sensing. The current–voltage (I–V) characteristics of Ag/HfO2/Si and Au/HfO2/Si devices under positive and negative bias conditions have provided valuable information on the ON and OFF states of the devices and the underlying resistive switching mechanisms. Repeatable, low-power, and forming-free bipolar resistive switching is obtained with both device structures, with the Au/HfO2/Si devices displaying a poorer device-to-device reproducibility. Furthermore, the Au/HfO2/Si devices have exhibited N-type negative differential resistance (NDR), suggesting Joule-heating activated migration of oxygen vacancies to be responsible for the SET process in the unstable unipolar mode.

ION TRACK-BASED NANOELECTRONICS

2005 ◽  
Vol 04 (05n06) ◽  
pp. 965-973 ◽  
Author(s):  
D. FINK ◽  
A.V. PETROV ◽  
W. R. FAHRNER ◽  
K. HOPPE ◽  
R. M. PAPALEO ◽  
...  
Keyword(s):  
Silicon Oxide ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Light Pressure ◽  
Alcohol Vapor ◽  
Ion Tracks ◽  
Aspect Ratios ◽  
Current Voltage ◽  
Polymer Foils ◽  
Novel Structures

In the last years, concepts have been developed to use etched ion tracks in insulators, such as polymer foils or silicon oxide layers as hosts for nano- and microelectronic structures. Depending on their etching procedure and the thickness of the insulating layer in which they are embedded, such tracks have typical diameters between some 10 nm and a few μm and lengths between some 100 nm and some 10 μm. Due to their extremely high aspect ratios, and due to the possibility to cover very large sample areas, they exceed the potential of nanolithography. In this paper, the strategies of etched ion track manipulation are briefly outlined, that lead to the formation of nanotubules, nanowires, or tubular arrangements of nanoclusters. Examples where nanoelectronic structures are based on single ion tracks, are nanocondensors or sensors for temperature, light, pressure, humidity and/or alcohol vapor. By combination of ion track metallization and conducting track-to-track connections on the foil surface, micromagnets, microtransformers and microcondensors could be formed within polymer foils. Finally, we present our new "TEMPOS" (Tunable Electronic Material with Pores in Oxide on Silicon) concept where nanometric pores, produced by etching of tracks in silicon oxide on silicon wafers, are used as charge extraction (or injection) channels. In comparison with the metal oxide semiconductor field effect transistors (MOS-FETs), the TEMPOS structures have a number of additional parameters (such as the track diameter, density, and shape, and the material embedded therein and its spatial distribution) which makes these novel structures much more complex. This eventually leads to higher compactation of the TEMPOS circuits and to unexpected electronic properties. TEMPOS structures can overtake the function of tunable resistors, condensors, photocells, hygrocells, diodes, sensors, and other elements. As an example, some corresponding current/voltage relations and TEMPOS circuits are presented. In this work we concentrate on TEMPOS structures with fullerene and phthalocyanine. Though not yet verified, TEMPOS structures could, in principle, be scaled down to nanometer sizes.

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