scholarly journals Design and Implementation of RF Front-End Module Based on 3D Heterogenous-Integrated Wafer-Level Packaging

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1893
Author(s):  
Faxin Yu ◽  
Qi Zhou ◽  
Zhiyu Wang ◽  
Jiongjiong Mo ◽  
Hua Chen

In this paper, a three-dimensional heterogenous-integrated (3DHI) wafer-level packaging (WLP) process is proposed, and a radio frequency (RF) front-end module with two independent ultra-high frequency (UHF) receiving channels are designed and implemented, which covers 400 MHz–600 MHz and 2050 MHz–2200 MHz respectively for unmanned aerial vehicle (UAV) applications. The module is formed by wafer-to-wafer (W2W) bonding of two high-resistivity silicon (HR-Si) interposers with embedded bare dies and through silicon via (TSV) interconnections. Double-sided deep reactive ion etching (DRIE) and conformal electroplating process are introduced to realize the high-aspect-ratio TSV connection within 290 µm-thick cap interposer. Co-plane waveguide (CPW) transmission lines are fabricated as the process control monitor (PCM), the measured insertion loss of which is less than 0.18 dB/mm at 35 GHz. The designed RF front-end module is fabricated and measured. The measured return loss and gain of each RF channel is better than 13 dB and 21 dB, and the noise figure is less than 1.5 dB. In order to evaluate the capability of the 3DHI process for multi-layer interposers, the module is re-designed and fabricated with four stacked high-resistivity silicon interposers. After W2W bonding of two pairs of interposers and wafer slicing, chip-to chip (C2C) bonding is applied to form a four-layer module with operable temperature gradient.

Author(s):  
Jong-Min Yook ◽  
Dongsu Kim ◽  
Bok-Ju Park ◽  
Sanghoon Sim ◽  
Yun-Seong Eo ◽  
...  

Author(s):  
Humberto Campanella ◽  
You Qian ◽  
Christian O. Romero ◽  
Jen Shuang Wong ◽  
Joan Giner ◽  
...  

ETRI Journal ◽  
2019 ◽  
Vol 41 (2) ◽  
pp. 262-269 ◽  
Author(s):  
Sangkil Kim ◽  
Amin Rida ◽  
Vasileios Lakafosis ◽  
Symeon Nikolaou ◽  
Manos M. Tentzeris

2006 ◽  
Vol 970 ◽  
Author(s):  
Ronald J. Gutmann ◽  
J. Jay McMahon ◽  
Jian-Qiang Lu

ABSTRACTA monolithic, wafer-level three-dimensional (3D) technology platform is described that is compatible with next-generation wafer level packaging (WLP) processes. The platform combines the advantages of both (1) high bonding strength and adaptability to IC wafer topography variations with spin-on dielectric adhesive bonding and (2) process integration and via-area advantages of metal-metal bonding. A copper-benzocyclobutene (Cu-BCB) process is described that incorporates single-level damascene-patterned Cu vias with partially-cured BCB as the bonding adhesive layer. A demonstration vehicle consisting of a two-wafer stack of 2-4 μm diameter vias has shown the bondability of both Cu-to-Cu and BCB-to-BCB. Planarization conditions to achieve BCB-BCB bonding with low-resistance Cu-Cu contacts have been examined, with wafer-scale planarization requirements compared to other 3D platforms. Concerns about stress induced at the tantalum (Ta) liner-to-BCB interface resulting in partial delamination are discussed. While across-wafer uniformity has not been demonstrated, the viability of this WLP-compatible 3D platform has been shown.


Author(s):  
Kun Wang ◽  
M. Frank ◽  
P. Bradley ◽  
R. Ruby ◽  
W. Mueller ◽  
...  

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