scholarly journals Floating Filler (FF) in an Indium Gallium Zinc Oxide (IGZO) Channel Improves the Erase Performance of Vertical Channel NAND Flash with a Cell-on-Peri (COP) Structure

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1561
Author(s):  
Seonjun Choi ◽  
Changhwan Choi ◽  
Jae Kyeong Jeong ◽  
Myounggon Kang ◽  
Yun-heub Song
Keyword(s):  
Work Function ◽  
Leakage Current ◽  
Device Simulation ◽  
Vertical Channel ◽  
Indium Gallium Zinc Oxide ◽  
Nand Flash ◽  
Optimum Conditions ◽  
A Cell ◽  
Current Reduction ◽  
P Type

In this study, we developed a V-NAND with an improved IGZO-P type (IP) floating filler (FF) structure based on an IGZO channel verified in previous studies and demonstrated that it has a very fast erase speed through device simulation. The proposed FF structure can supply holes generated through the Gate-Induced Drain Leakage (GIDL) phenomenon in the upper polysilicon string select line (SSL) channel to the IGZO channel through a P-type filler, and the structure proposed by this operation shows a very fast erase speed of 4 μs. A fast erase speed was achieved because the filler adjacent to the IGZO channel, like IP structures in previous studies, functioned as a path through which electrons emitted from the charge storage layer moved easily, rather than simply supplying holes. This assumption was confirmed by assessing the change in electron density of the channel during the erase operation. Next, we investigated the optimum conditions for leakage current reduction through various condition changes of the lower ground select line (GSL) gate in the proposed structure. We confirmed that the leakage current of the proposed structure can be minimized by changing the number of lower GSL gates, changing the length of the GSL channel, and/or changing the work function of the GSL gate material. We obtained a leakage current of 10−17 A when the GSL channel was 480 nm long with six GSL gates, each with a length of 40 nm. The work function of the gates was 4.96 eV.

Vertical Conduction in the New Field Effect Transistors: p-Type and n-Type Vertical Channel Thin Film Transistors

2014 ◽  
Vol 23 (03n04) ◽  
pp. 1450023 ◽  
Author(s):  
Olivier Bonnaud ◽  
Peng Zhang ◽  
Emmanuel Jacques ◽  
Regis Rogel
Keyword(s):  
Thin Film ◽  
Leakage Current ◽  
Thin Film Transistors ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Substrate Surface ◽  
Vertical Channel ◽  
Electrical Behavior ◽  
Research Activities ◽  
P Type

In order to pursue the integration, the research activities were oriented during the last years towards channel conduction in a plan perpendicular to the substrate surface while in the traditional architectures the conduction is parallel to the surface, under the gate. In the integrated technologies, this approach led to the FinFET. But in this case, even though the conduction plan is perpendicular to the substrate surface, the direction of the drain currents remains parallel to the substrate. New electronics devices were designed with the channels vertically oriented. In the monolithic technologies, many drawbacks have stopped this trend. However, in the case of thin film technologies, the approach appeared more suitable. The channel conduction is thus vertically oriented. But a drawback comes from the leakage current flowing between source and drain. The introduction of an insulating barrier in-between and the decrease of the thickness of the channel active layer, led to electrical behavior much more suitable for applications. After an overview of the different approaches developed as well in monolithic technologies as in thin film technologies, this presentation will give details on the concept and on the fabrication process of quasi-vertical thin film transistors. The associated electrical results will be described, analyzed and commented.

scholarly journals A Novel Structure and Operation Scheme of Vertical Channel NAND Flash with Ferroelectric Memory for Multi String Operations

Electronics ◽  
2020 ◽  
Vol 10 (1) ◽  
pp. 32
Author(s):  
Seonjun Choi ◽  
Changhwan Choi ◽  
Jae Kyeong Jeong ◽  
Myounggon Kang ◽  
Yun-heub Song
Keyword(s):  
Device Simulation ◽  
Vertical Channel ◽  
The Other ◽  
Hole Density ◽  
Nand Flash ◽  
Voltage Difference ◽  
Operation Method ◽  
Novel Structure ◽  
Ferroelectric Memory ◽  
Selective Program

In this study, the operation method of the proposed ferroelectric memory structure as a method to overcome the limitations of the existing Charge Trap Flash (CTF) memory Vertical NAND (V-NAND) structure was presented and verified through device simulation. The proposed structure and operation method applied the BiCS (Bit Cost Scalable) structure GIDL (Gate Induce Drain Leakage) deletion method to confirm that selective program operation is possible in the ferroelectric memory V-NAND (Vertical Channel NAND) structure. In particular, we confirmed that the proposed method can easily suppress the program operation by adjusting the hole density of the channel even in the “Y-mode” operation. The channel hole density adjustment that makes this possible can be easily controlled by the voltage difference between the bit line (BL) and drain select line (DSL) contacts. The proposed structure was verified through a device simulation, and as a result of the verification, it was confirmed that the channel hole can be selectively charged in the program operation. Through this, when the cell to be programmed shows the program operation of 2.3 V, the other cells do not. It was confirmed that it could be suppressed to 0.4 V.

Leakage Current Reduction of Ni-MILC Poly-Si TFT Using Chemical Cleaning Method

2018 ◽  
Vol 28 (8) ◽  
pp. 440-444
Author(s):  
Kwang-Jin Lee ◽  
◽  
Doyeon Kim ◽  
Duck-Kyun Choi ◽  
Woo-Byoung Kim
Keyword(s):  
Leakage Current ◽  
Chemical Cleaning ◽  
Cleaning Method ◽  
Current Reduction

Organic synaptic devices based on ionic gel with reduced leakage current

2021 ◽  
Vol 57 (15) ◽  
pp. 1907-1910
Author(s):  
Dapeng Liu ◽  
Yiwei Zhao ◽  
Qianqian Shi ◽  
Shilei Dai ◽  
Li Tian ◽  
...  
Keyword(s):  
Solid State ◽  
Leakage Current ◽  
Dielectric Film ◽  
Neuromorphic Computing ◽  
Computing Systems ◽  
Current Reduction

A solid-state hybrid electrolyte dielectric film was designed for leakage current reduction, synaptic simulation and neuromorphic computing systems.

A Single-Phase Five-Level Transformer-Less PV Inverter for Leakage Current Reduction

2021 ◽  
pp. 1-1
Author(s):  
Xiaonan Zhu ◽  
Hongliang Wang ◽  
Wenyuan Zhang ◽  
Hanzhe Wang ◽  
Xiaojun Deng ◽  
...  
Keyword(s):  
Leakage Current ◽  
Single Phase ◽  
Pv Inverter ◽  
Current Reduction

scholarly journals The use of a slide spinner in the analysis of cell dispersion.

1976 ◽  
Vol 24 (1) ◽  
pp. 11-15 ◽  
Author(s):  
R C Wolley ◽  
H M Dembitzer ◽  
F Herz ◽  
K Schreiber ◽  
L G Koss
Keyword(s):  
Cell Suspension ◽  
Single Cells ◽  
Cell Loss ◽  
Optimum Conditions ◽  
Isolated Cells ◽  
Cell Dispersion ◽  
Cervical Cancer Cells ◽  
A Cell ◽  
Human Cervical Cancer Cells ◽  
Human Cervical Cancer

A simple and reliable method of determining the degree of dispersion of a cell suspension has been developed using the Perkin-Elmer Uni-Smear Spinner. Optimum conditions regarding rate and duration of spin, etc., were first ascertained using dispersed cell cultures including human cervical cancer cells as well as gynecologic samples. After spinning, single cells in suspension appeared as isolated cells on the slides. Cell aggregates, on the other hand, remained together. Therefore, the distribution of cells in various sized aggregates could be easily quantitated and the slides retained for future review. This method was used to evaluate the dispersing effects of trypsin, ethylenediaminetetraacetate and and syringing human on human gynecology samples obtained by routine cervical scrapes. None of the dispersion methods has, so far, produced an adequate monodispersed cell suspension without unacceptable cell loss.

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