scholarly journals TSPEM Parameter Extraction Method and Its Applications in the Modeling of Planar Schottky Diode in THz Band

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1540
Author(s):  
Xiaoyu Liu ◽  
Yong Zhang ◽  
Haoran Wang ◽  
Luwei Qi ◽  
Bo Wang ◽  
...  
Keyword(s):  
Extraction Method ◽  
Schottky Diodes ◽  
Three Dimensional ◽  
Parameter Extraction ◽  
Frequency Multiplier ◽  
Junction Capacitance ◽  
Capacitance Extraction ◽  
Electromagnetic Model ◽  
Measurement Results ◽  
Parasitic Parameters

In this paper, a new method for the parameter extraction of Schottky barrier diode (SBD) is presented to eliminate the influence of parasitic parameters on the intrinsic capacitance-voltage (C-V) characteristics of the Schottky diodes at high frequencies. The method is divided into the de-embedding and parameter extraction, including six auxiliary configurations and, is referred tos as Two-step Six-configuration Parameter Extraction Method (TSPEM). Compared to the traditional junction capacitance extraction method, this method can extract the value of junction capacitance at higher frequencies with higher accuracy. At the same time, compared to the other de-embedding methods, this method shows better performance in de-embedding the contributions of parasitic structures from the transmission line measurements. The intrinsic junction capacitances obtained by this method and the three-dimensional (3-D) electromagnetic model are combined to form a diode simulation model, which accurately characterizes the capacitance characteristics of the SBD. It was verified with a 200 GHz double frequency multiplier, and the simulation results and measurement results showed good consistency.

Interconnect Capacitance Extraction in Large-Area a-Si Imaging Systems

1998 ◽  
Vol 507 ◽  
Author(s):  
H.H. Pham ◽  
A. Nathan
Keyword(s):  
Thin Film Transistors ◽  
Extraction Method ◽  
Three Dimensional ◽  
Imaging Systems ◽  
Computational Technique ◽  
Floating Potential ◽  
Large Area ◽  
Capacitance Extraction ◽  
Exponential Expansion ◽  
Si Thin Film

ABSTRACTWe present a new numerical extraction method for the quasi-static parasitic coupling capacitances associated with geometric overlapping in amorphous silicon (a-Si) thin film transistors (TFTs) and interconnect addressing lines in large-area a-Si imaging systems. The capacitance is extracted using a recently developed computational technique, based on exponential expansion of the Green's function, which offers a quick and accurate means of computing the three-dimensional potential and electric field, and hence, the charge distribution and capacitance. The technique can be used for effectively dealing with the extreme geometry TFT and interconnect structures (where layer thicknesses are much smaller than the other physical dimensions), the floating potential of the glass substrate, and multidielectric media, all of which are typical to large-area a-Si imaging electronics.

Capacitance extraction method for a free-standing bilayer lipid membrane formed over an aperture in a nanofabricated silicon chip

2020 ◽  
Vol 59 (SI) ◽  
pp. SIIK02
Author(s):  
Yasutaka Tomioka ◽  
Shogo Takashima ◽  
Masataka Moriya ◽  
Hiroshi Shimada ◽  
Fumihiko Hirose ◽  
...  
Keyword(s):  
Extraction Method ◽  
Lipid Membrane ◽  
Bilayer Lipid Membrane ◽  
Free Standing ◽  
Capacitance Extraction ◽  
Bilayer Lipid
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