scholarly journals Ring-Oscillator with Multiple Transconductors for Linear Analog-to-Digital Conversion

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1408
Author(s):  
Leidy Mabel Alvero-Gonzalez ◽  
Victor Medina ◽  
Vahur Kampus ◽  
Susana Paton ◽  
Luis Hernandez ◽  
...  
Keyword(s):  
Input Voltage ◽  
Open Loop ◽  
Ring Oscillator ◽  
Frequency Function ◽  
Cmos Process ◽  
Analog To Digital ◽  
Analog To Digital Conversion ◽  
Voltage Signal ◽  
Iot Devices ◽  
Loop Ring

This paper proposes a new circuit-based approach to mitigate nonlinearity in open-loop ring-oscillator-based analog-to-digital converters (ADCs). The approach consists of driving a current-controlled oscillator (CCO) with several transconductors connected in parallel with different bias conditions. The current injected into the oscillator can then be properly sized to linearize the oscillator, performing the inverse current-to-frequency function. To evaluate the approach, a circuit example has been designed in a 65-nm CMOS process, leading to a more than 3-ENOB enhancement in simulation for a high-swing differential input voltage signal of 800-mVpp, with considerable less complex design and lower power and expected area in comparison to state-of-the-art circuit based solutions. The architecture has also been checked against PVT and mismatch variations, proving to be highly robust, requiring only very simple calibration techniques. The solution is especially suitable for high-bandwidth (tens of MHz) medium-resolution applications (10–12 ENOBs), such as 5G or Internet-of-Things (IoT) devices.

scholarly journals Design of Bootstrap Sample and Hold Circuit

2019 ◽  
Vol 8 (4) ◽  
pp. 4053-4057
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Performance Metrics ◽  
Open Loop ◽  
Cmos Process ◽  
Bootstrap Sample ◽  
Analog To Digital ◽  
Sample And Hold ◽  
Higher Power ◽  
The Cost

This paper describes the design and implementation of open loop sample and hold circuit using bootstrap technique, which can be used as front end sampling circuit for high speed analog-to-digital converters. Different design criteria viz. speed, power, resolution, linearity, noise and harmonic analysis have been dealt with. Both theoretical analysis and simulation results are carried out. The bootstrap circuit is designed and then compared in a 0.18μm and 0.35μm CMOS process. It is observed that signal to noise and distortion ratio (SNDR) and effective number of bits (ENOB) are higher for 0.35µm technology. But these advantages are at the cost of higher power dissipation. Hence there exists a trade-off between these performance metrics.

The Research of CNC Constant Voltage Power

2013 ◽  
Vol 475-476 ◽  
pp. 1670-1673
Author(s):  
Shi Wei Lin
Keyword(s):  
Pulse Width ◽  
Pulse Width Modulation ◽  
Short Circuit ◽  
Input Voltage ◽  
Constant Voltage ◽  
Digital Conversion ◽  
Power Circuit ◽  
Analog To Digital ◽  
Analog To Digital Conversion ◽  
Driver Amplifier

CNC constant voltage power is composed by the analog power circuit, MCU control circuit , pulse width modulation circuit, a power driver amplifier , analog to digital conversion circuit , the input voltage setting circuit and the output voltage display circuit. The power possesses the functions of digital regulator, high precision output, short-circuit & over-current protection and alarm functions, especially for a higher accuracy requirements for various occasions.

Readout Integrated Circuits with Pixel-Level ADC for Ultraviolet FPA Applications

2012 ◽  
Vol 229-231 ◽  
pp. 1499-1502
Author(s):  
Bin Xu ◽  
Yong Gang Yuan ◽  
Ding Ma ◽  
Neng Bin Cai ◽  
Xiang Yang Li
Keyword(s):  
Integrated Circuits ◽  
Dynamic Range ◽  
Cmos Process ◽  
Low Light ◽  
Digital Conversion ◽  
Analog To Digital ◽  
Multiple Channel ◽  
Analog To Digital Conversion ◽  
Pixel Sensors ◽  
Digital Pixel

An array of 128×128 digital pixel sensors (DPS) that performs both in pixel light current integration and analog-to-digital conversion is presented. The pixel fabricated on a DP4M CMOS process provides a digital output of ultraviolet light intensity via an integrated multiple-channel bit-serial (MCBS) ADC. Due to low light current (~pA) of ultraviolet focal-plane-array, the architecture of capacitive trans-impedance amplifier (CTIA) is used. The proposed readout integrated circuits have a 12-bit resolution, 70dB dynamic range and 99% of linearity.

A Computationally Efficient Visual Saliency Algorithm Suitable for an Analog CMOS Implementation

2018 ◽  
Vol 30 (9) ◽  
pp. 2439-2471 ◽  
Author(s):  
Robert D'Angelo ◽  
Richard Wood ◽  
Nathan Lowry ◽  
Geremy Freifeld ◽  
Haiyao Huang ◽  
...  
Keyword(s):  
Visual Saliency ◽  
Pulse Mode ◽  
System Level ◽  
Cmos Process ◽  
Computationally Efficient ◽  
Analog To Digital ◽  
Analog Cmos ◽  
Cmos Design ◽  
Analog To Digital Conversion ◽  
Cmos Image Sensors

Computer vision algorithms are often limited in their application by the large amount of data that must be processed. Mammalian vision systems mitigate this high bandwidth requirement by prioritizing certain regions of the visual field with neural circuits that select the most salient regions. This work introduces a novel and computationally efficient visual saliency algorithm for performing this neuromorphic attention-based data reduction. The proposed algorithm has the added advantage that it is compatible with an analog CMOS design while still achieving comparable performance to existing state-of-the-art saliency algorithms. This compatibility allows for direct integration with the analog-to-digital conversion circuitry present in CMOS image sensors. This integration leads to power savings in the converter by quantizing only the salient pixels. Further system-level power savings are gained by reducing the amount of data that must be transmitted and processed in the digital domain. The analog CMOS compatible formulation relies on a pulse width (i.e., time mode) encoding of the pixel data that is compatible with pulse-mode imagers and slope based converters often used in imager designs. This letter begins by discussing this time-mode encoding for implementing neuromorphic architectures. Next, the proposed algorithm is derived. Hardware-oriented optimizations and modifications to this algorithm are proposed and discussed. Next, a metric for quantifying saliency accuracy is proposed, and simulation results of this metric are presented. Finally, an analog synthesis approach for a time-mode architecture is outlined, and postsynthesis transistor-level simulations that demonstrate functionality of an implementation in a modern CMOS process are discussed.

scholarly journals A VCO-Based CMOS Readout Circuit for Capacitive MEMS Microphones

Sensors ◽  
2019 ◽  
Vol 19 (19) ◽  
pp. 4126 ◽  
Author(s):  
Andres Quintero ◽  
Fernando Cardes ◽  
Carlos Perez ◽  
Cesare Buffa ◽  
Andreas Wiesbauer ◽  
...  
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Readout Circuit ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Mems Microphone ◽  
Mems Microphones

Microelectromechanical systems (MEMS) microphone sensors have significantly improved in the past years, while the readout electronic is mainly implemented using switched-capacitor technology. The development of new battery powered “always-on” applications increasingly requires a low power consumption. In this paper, we show a new readout circuit approach which is based on a mostly digital Sigma Delta ( Σ Δ ) analog-to-digital converter (ADC). The operating principle of the readout circuit consists of coupling the MEMS sensor to an impedance converter that modulates the frequency of a stacked-ring oscillator—a new voltage-controlled oscillator (VCO) circuit featuring a good trade-off between phase noise and power consumption. The frequency coded signal is then sampled and converted into a noise-shaped digital sequence by a time-to-digital converter (TDC). A time-efficient design methodology has been used to optimize the sensitivity of the oscillator combined with the phase noise induced by 1 / f and thermal noise. The circuit has been prototyped in a 130 nm CMOS process and directly bonded to a standard MEMS microphone. The proposed VCO-based analog-to-digital converter (VCO-ADC) has been characterized electrically and acoustically. The peak signal-to-noise and distortion ratio (SNDR) obtained from measurements is 77.9 dB-A and the dynamic range (DR) is 100 dB-A. The current consumption is 750 μ A at 1.8 V and the effective area is 0.12 mm 2 . This new readout circuit may represent an enabling advance for low-cost digital MEMS microphones.

scholarly journals Design an Improved Structure for 10-Bit Pipeline Analog to Digital Converter Based on 0.18µm CMOS Technology

2019 ◽  
Vol 9 (2) ◽  
pp. 169-176
Author(s):  
Arash Rezapour ◽  
Farbod Setoudeh ◽  
Mohammad Bagher Tavakoli
Keyword(s):  
Data Transfer ◽  
Input Voltage ◽  
Cmos Technology ◽  
Open Loop ◽  
Total Power ◽  
Analog To Digital ◽  
Second Stage ◽  
Novel Structure ◽  
Total Power Consumption ◽  
Two Stages

Abstract This paper proposed a novel structure of a 10-bit, 400MS/s pipelined analog to digital convertor using 0.18 µm TSMC technology. In this paper, two stages are used to converter design and a new method is proposed to increase the speed of the pipeline analog to digital convertor. For this purpose, the amplifier is not used at the first stage and the buffer is used for data transfer to the second stage, in the second stage an amplifier circuit with accurate gain of 8 that is open loop with a new structure was used to speed up, also the design is such that the first 4 bits are extracted simultaneously with sampling. On the other hand, in this structure, since in the first stage the information is not amplified and transferred to the second stage, the accuracy of the comparator circuit should be high, therefore a new structure is proposed to design a comparator circuit that can detect unwanted offsets and eliminate them without delay, and thus can detect the smallest differences in input voltage. The proposed analog to digital convertor was designed with a resolution of 10 bits and a speed of 400MS/s, with the total power consumption 74.3mW using power supply of 1.8v.

Comparison of Dc-Dc SEPIC, CUK and Flyback Converters Based LED Drivers

2020 ◽  
pp. 99-107
Author(s):  
Erdal Sehirli
Keyword(s):  
Integrated Circuit ◽  
Closed Loop ◽  
Input Voltage ◽  
Open Loop ◽  
Current Sensor ◽  
Switching Frequency ◽  
Led Driver ◽  
Advantages And Disadvantages ◽  
Led Drivers ◽  
Conduction Mode

This paper presents the comparison of LED driver topologies that include SEPIC, CUK and FLYBACK DC-DC converters. Both topologies are designed for 8W power and operated in discontinuous conduction mode (DCM) with 88 kHz switching frequency. Furthermore, inductors of SEPIC and CUK converters are wounded as coupled. Applications are realized by using SG3524 integrated circuit for open loop and PIC16F877 microcontroller for closed loop. Besides, ACS712 current sensor used to limit maximum LED current for closed loop applications. Finally, SEPIC, CUK and FLYBACK DC-DC LED drivers are compared with respect to LED current, LED voltage, input voltage and current. Also, advantages and disadvantages of all topologies are concluded.

Energy Harvesting via Analog-to-Digital Conversion

2021 ◽  
Author(s):  
Neha Jain ◽  
Nir Shlezinger ◽  
Yonina C. Eldar ◽  
Anubha Gupta ◽  
Vivek Ashok Bohara
Keyword(s):  
Energy Harvesting ◽  
Digital Conversion ◽  
Analog To Digital ◽  
Analog To Digital Conversion

A High-Speed Temperature Sensor with Low Supply Sensitivity for SoC Thermal Monitoring

2018 ◽  
Vol 27 (07) ◽  
pp. 1850116
Author(s):  
Yuanxin Bao ◽  
Wenyuan Li
Keyword(s):  
Temperature Sensor ◽  
Conversion Rate ◽  
High Speed ◽  
Supply Voltage ◽  
Ring Oscillator ◽  
Temperature Sensitive ◽  
Cmos Process ◽  
Digital Code ◽  
Thermal Monitoring ◽  
Worst Case

A high-speed low-supply-sensitivity temperature sensor is presented for thermal monitoring of system on a chip (SoC). The proposed sensor transforms the temperature to complementary to absolute temperature (CTAT) frequency and then into digital code. A CTAT voltage reference supplies a temperature-sensitive ring oscillator, which enhances temperature sensitivity and conversion rate. To reduce the supply sensitivity, an operational amplifier with a unity gain for power supply is proposed. A frequency-to-digital converter with piecewise linear fitting is used to convert the frequency into the digital code corresponding to temperature and correct nonlinearity. These additional characteristics are distinct from the conventional oscillator-based temperature sensors. The sensor is fabricated in a 180[Formula: see text]nm CMOS process and occupies a small area of 0.048[Formula: see text]mm2 excluding bondpads. After a one-point calibration, the sensor achieves an inaccuracy of [Formula: see text][Formula: see text]1.5[Formula: see text]C from [Formula: see text]45[Formula: see text]C to 85[Formula: see text]C under a supply voltage of 1.4–2.4[Formula: see text]V showing a worst-case supply sensitivity of 0.5[Formula: see text]C/V. The sensor maintains a high conversion rate of 45[Formula: see text]KS/s with a fine resolution of 0.25[Formula: see text]C/LSB, which is suitable for SoC thermal monitoring. Under a supply voltage of 1.8[Formula: see text]V, the maximum energy consumption per conversion is only 7.8[Formula: see text]nJ at [Formula: see text]45[Formula: see text]C.

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