scholarly journals VLSI Implementation of a Cost-Efficient Loeffler DCT Algorithm with Recursive CORDIC for DCT-Based Encoder

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 862
Author(s):  
Rih-Lung Chung ◽  
Chen-Wei Chen ◽  
Chiung-An Chen ◽  
Patricia Angela R. Abu ◽  
Shih-Lun Chen
Keyword(s):  
Image Quality ◽  
Power Consumption ◽  
Large Scale ◽  
Low Cost ◽  
Vlsi Implementation ◽  
Operating Frequency ◽  
Cmos Process ◽  
Scale Factors ◽  
Gate Count ◽  
Cost Efficient

This paper presents a low-cost and high-quality, hardware-oriented, two-dimensional discrete cosine transform (2-D DCT) signal analyzer for image and video encoders. In order to reduce memory requirement and improve image quality, a novel Loeffler DCT based on a coordinate rotation digital computer (CORDIC) technique is proposed. In addition, the proposed algorithm is realized by a recursive CORDIC architecture instead of an unfolded CORDIC architecture with approximated scale factors. In the proposed design, a fully pipelined architecture is developed to efficiently increase operating frequency and throughput, and scale factors are implemented by using four hardware-sharing machines for complexity reduction. Thus, the computational complexity can be decreased significantly with only 0.01 dB loss deviated from the optimal image quality of the Loeffler DCT. Experimental results show that the proposed 2-D DCT spectral analyzer not only achieved a superior average peak signal–noise ratio (PSNR) compared to the previous CORDIC-DCT algorithms but also designed cost-efficient architecture for very large scale integration (VLSI) implementation. The proposed design was realized using a UMC 0.18-μm CMOS process with a synthesized gate count of 8.04 k and core area of 75,100 μm2. Its operating frequency was 100 MHz and power consumption was 4.17 mW. Moreover, this work had at least a 64.1% gate count reduction and saved at least 22.5% in power consumption compared to previous designs.

scholarly journals A Smart Floating Gate Transistor with Two Control Gates for Active Noise Control

Micromachines ◽  
2019 ◽  
Vol 10 (11) ◽  
pp. 722
Author(s):  
Mao ◽  
Yang ◽  
Ma ◽  
Yan ◽  
Zhang
Keyword(s):  
Large Scale ◽  
Noise Control ◽  
Low Cost ◽  
Active Noise Control ◽  
Complementary Metal Oxide Semiconductor ◽  
Floating Gate ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Active Noise ◽  
Floating Gate Transistor

A smart floating gate transistor with two control gates was proposed for active noise control in bioelectrical signal measurement. The device, which is low cost and capable of large-scale integration, was implemented in a standard single-poly complementary metal–oxide–semiconductor (CMOS) process. A model of the device was developed to demonstrate the working principle. Theoretical analysis and simulation results proved the superposition of the two control gates. A series of test experiments were carried out and the results showed that the device was in accordance with the basic electrical characteristics of a floating gate transistor, including the current–voltage (I–V) characteristics and the threshold characteristics observed on the two control gates. Based on the source follower circuit, the experimental results proved that the device can reduce interference by more than 29 dB, which demonstrates the feasibility of the proposed device for active noise control.

High Speed Min/Max Architecture Based on a Novel Comparator in 0.18-μm CMOS Process

2015 ◽  
Vol 24 (04) ◽  
pp. 1550048 ◽  
Author(s):  
Amir Fathi ◽  
Abdollah Khoei ◽  
Khayrollah Hadidi
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Current Mode ◽  
Cmos Technology ◽  
Operating Frequency ◽  
Cmos Process ◽  
Fuzzy Logic Controllers ◽  
Speed Performance ◽  
External Clock ◽  
Frequency Feature

This paper describes the design of a high speed min/max architecture based on a new current comparator. The main advantage of the proposed circuit which employs a novel preamplifier-latch comparator is the higher operating frequency feature in comparison with previous works. Because the comparator can work in voltage mode, the min/max structure can be redesigned either in voltage or current mode. The designed comparator is refreshed without any external clock. Therefore, it does not degrade the speed performance of proposed min/max structure. These features along with low power consumption qualify the proposed architecture to be widely used in high speed fuzzy logic controllers (FLCs). Post-layout simulation results confirm 3.4 GS/s comparison rate with 9-bit resolution for a 0.9 V peak-to-peak input signal range for the comparator and 800 MHz operating frequency for min/max circuit. The power consumption of whole structure is 912 μW from a 1.8 V power supply using TSMC 0.18-μm CMOS technology.

scholarly journals Characterization of Shallow Whole-Metagenome Shotgun Sequencing as a High-Accuracy and Low-Cost Method by Complicated Mock Microbiomes

2021 ◽  
Vol 12 ◽  
Author(s):  
Wenyi Xu ◽  
Tianda Chen ◽  
Yuwei Pei ◽  
Hao Guo ◽  
Zhuanyu Li ◽  
...  
Keyword(s):  
Large Scale ◽  
Low Cost ◽  
Bacterial Species ◽  
Amplicon Sequencing ◽  
Shotgun Sequencing ◽  
Taxonomic Resolution ◽  
Rrna Gene ◽  
Cost Efficient ◽  
Taxonomic Assignments

Characterization of the bacterial composition and functional repertoires of microbiome samples is the most common application of metagenomics. Although deep whole-metagenome shotgun sequencing (WMS) provides high taxonomic resolution, it is generally cost-prohibitive for large longitudinal investigations. Until now, 16S rRNA gene amplicon sequencing (16S) has been the most widely used approach and usually cooperates with WMS to achieve cost-efficiency. However, the accuracy of 16S results and its consistency with WMS data have not been fully elaborated, especially by complicated microbiomes with defined compositional information. Here, we constructed two complex artificial microbiomes, which comprised more than 60 human gut bacterial species with even or varied abundance. Utilizing real fecal samples and mock communities, we provided solid evidence demonstrating that 16S results were of poor consistency with WMS data, and its accuracy was not satisfactory. In contrast, shallow whole-metagenome shotgun sequencing (shallow WMS, S-WMS) with a sequencing depth of 1 Gb provided outputs that highly resembled WMS data at both genus and species levels and presented much higher accuracy taxonomic assignments and functional predictions than 16S, thereby representing a better and cost-efficient alternative to 16S for large-scale microbiome studies.

scholarly journals The Implementation of a 2/4/8 Antennas Configurable Diversity OFDM Receiver for Mobile HDTV Application

2009 ◽  
Vol 2009 ◽  
pp. 1-9 ◽  
Author(s):  
Jing Gao ◽  
Takashi Iida ◽  
Hiroyuki Mizutani ◽  
Sadanori Sakaguchi ◽  
Shuji Murakami ◽  
...  
Keyword(s):  
Power Consumption ◽  
Rayleigh Fading ◽  
Low Cost ◽  
Digital Tv ◽  
Adaptive Array ◽  
Cmos Process ◽  
Antenna Diversity ◽  
Diversity Combining ◽  
Reception System ◽  
Diversity Receiver

Two pre-FFT adaptive array (AA) antenna combiners and a post-FFT carrier diversity (CD) combiner are integrated with a Japan Terrestrial digital TV (ISDB-T) OFDM receiver using 90 nm 7M1P CMOS process. A 2/4/8-antenna diversity receiver can be configured and a low-cost 4 antenna diversity reception system can be realized in one LSI by making use of the AA-CD two-stage diversity combining method. Mobile reception performance is increased by 1.63 times using a denoise filter circuit and SPLINE interpolator under urban 6-path Rayleigh fading (TU6) model with 2-antenna post-FFT carrier diversity (2CD) combing mode. The die area is 49  and the power consumption is 310 mW.

scholarly journals Joint QoS-aware and Cost-efficient Task Scheduling for Fog-cloud Resources in a Volunteer Computing System

2021 ◽  
Vol 21 (4) ◽  
pp. 1-21
Author(s):  
Farooq Hoseiny ◽  
Sadoon Azizi ◽  
Mohammad Shojafar ◽  
Rahim Tafazolli
Keyword(s):  
Task Scheduling ◽  
Large Scale ◽  
Low Cost ◽  
Computing System ◽  
Volunteer Computing ◽  
Processing Power ◽  
Np Hard Problem ◽  
Cost Efficient ◽  
Data Transferring ◽  
Cloud Resources

Volunteer computing is an Internet-based distributed computing in which volunteers share their extra available resources to manage large-scale tasks. However, computing devices in a Volunteer Computing System (VCS) are highly dynamic and heterogeneous in terms of their processing power, monetary cost, and data transferring latency. To ensure both of the high Quality of Service (QoS) and low cost for different requests, all of the available computing resources must be used efficiently. Task scheduling is an NP-hard problem that is considered as one of the main critical challenges in a heterogeneous VCS. Due to this, in this article, we design two task scheduling algorithms for VCSs, named Min-CCV and Min-V . The main goal of the proposed algorithms is jointly minimizing the computation, communication, and delay violation cost for the Internet of Things (IoT) requests. Our extensive simulation results show that proposed algorithms are able to allocate tasks to volunteer fog/cloud resources more efficiently than the state-of-the-art. Specifically, our algorithms improve the deadline satisfaction task rates around 99.5% and decrease the total cost between 15 to 53% in comparison with the genetic-based algorithm.

scholarly journals A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits

Sensors ◽  
2021 ◽  
Vol 21 (13) ◽  
pp. 4462
Author(s):  
Malik Summair Asghar ◽  
Saad Arslan ◽  
HyungWon Kim
Keyword(s):  
Neural Network ◽  
Power Consumption ◽  
Large Scale ◽  
Average Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Input Image ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Spiking Neural Network ◽  
Digital Implementation

To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Complementary Metal Oxide Semiconductor (CMOS) implementation incorporates neuron and synaptic circuits optimized for area and power consumption. The asynchronous neuronal circuits implemented benefit from higher energy efficiency and higher sensitivity. The proposed synapse circuit based on Binary Exponential Charge Injector (BECI) saves area and power consumption, and provides design scalability for higher resolutions. The SNN model implemented is optimized for 9 × 9 pixel input image and minimum bit-width weights that can satisfy target accuracy, occupies less area and power consumption. Moreover, the spiking neural network is replicated in full digital implementation for area and power comparisons. The SNN chip integrated from neuron and synapse circuits is capable of pattern recognition. The proposed SNN chip is fabricated using 180 nm CMOS process, which occupies a 3.6 mm2 chip core area, and achieves a classification accuracy of 94.66% for the MNIST dataset. The proposed SNN chip consumes an average power of 1.06 mW—20 times lower than the digital implementation.

Design a Phase Frequency Detector

2013 ◽  
Vol 380-384 ◽  
pp. 3198-3203
Author(s):  
Xue Mei Lei ◽  
Xiao Dong Xing ◽  
Xue Dong Ding
Keyword(s):  
Power Consumption ◽  
Core Area ◽  
Operating Frequency ◽  
Cmos Process ◽  
Flip Flop ◽  
Phase Frequency Detector ◽  
High Frequencies ◽  
The Core ◽  
Input Signals ◽  
Frequency Detector

This paper describes a phase frequency detector application using 0.18μm CMOS process. In order to cover the high frequencies of input signals, TSPC D flip-flop structure are applied. The core area of proposal phase frequency detector is 60 μm×50 μm. The simulating results show that rang of operating frequency is from 500kHz to 500MHz and the power consumption is 0.722mW under a 1.8V supply.

scholarly journals VERY LARGE SCALE INTEGRATION TINY CHIP WITH NANOPOWER SENSOR APPLICATIONS

2012 ◽  
pp. 116-120
Author(s):  
K.JAYA SWAROOP ◽  
M.I. SUDHARAYAPPA ◽  
CH. JAYAPRAKASH ◽  
V.SURENDRA BABU
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
Large Scale ◽  
Supply Voltage ◽  
Vlsi Design ◽  
Electrical Characterization ◽  
Cmos Process ◽  
Process Technology ◽  
Voltage Range ◽  
Sensor Applications

Semiconductor devices have rapidly advanced over the past years increasing switching(on and off) speed and density of the device, causing an increase in power consumption and power dissipation; accordingly, the issues have been considered and improved . In CMOS 0.5μm process, the designed VLSI mirror-amplifier had power dissipation of 8.41 milliwatts. This technique is changed in this paper. The biasing is done in two steps proved to be correct procedure to improve overall power consumption. Source voltage was considered as 3V for the MOSIS process technology. Layout ,simulation and electrical characterization of the design were carried out by MENTOR GRAPHICS tool and CAD tools were used for the design Holding the scaling and process unchanged at 0.5μm as the previous design, the new VLSI design had power dissipation of 4.39 nanowatts in second step by reducing the dynamic loss. Multi-die chip placement is done for fabrication. More advanced 0.35um CMOS process is used for low threshold voltage and enhanced supply voltage range. This paper presents details of the key research works, results, completed chip layout and applications of the chip.

scholarly journals Low-Power RFED Wake-Up Receiver Design for Low-Cost Wireless Sensor Network Applications

Sensors ◽  
2020 ◽  
Vol 20 (22) ◽  
pp. 6406
Author(s):  
David Galante-Sempere ◽  
Dailos Ramos-Valido ◽  
Sunil Lalchand Khemchandani ◽  
Javier del Pino
Keyword(s):  
Power Consumption ◽  
Low Cost ◽  
Sensor Nodes ◽  
Wireless Sensor ◽  
Cmos Process ◽  
Receiver Design ◽  
High Integrability ◽  
Active Components ◽  
Total Size ◽  
Area Reduction

The development of wake-up receivers (WuR) has recently received a lot of interest from both academia and industry researchers, primarily because of their major impact on the improvement of the performance of wireless sensor networks (WSNs). In this paper, we present the development of three different radiofrequency envelope detection (RFED) based WuRs operating at the 868 MHz industrial, scientific and medical (ISM) band. These circuits can find application in densely populated WSNs, which are fundamental components of Internet-of-Things (IoT) or Internet-of-Everything (IoE) applications. The aim of this work is to provide circuits with high integrability and a low cost-per-node, so as to facilitate the implementation of sensor nodes in low-cost IoT applications. In order to demonstrate the feasibility of implementing a WuR with commercially available off-chip components, the design of an RFED WuR in a PCB mount is presented. The circuit is validated in a real scenario by testing the WuR in a system with a pattern recognizer (AS3933), an MCU (MSP430G2553 from TI), a transceiver (CC1101 from TI) and a T/R switch (ADG918). The WuR has no active components and features a sensitivity of about −50 dBm, with a total size of 22.5 × 51.8 mm2. To facilitate the integration of the WuR in compact systems and low-cost applications, two designs in a commercial UMC 65 nm CMOS process are also explored. Firstly, an RFED WuR with integrated transformer providing a passive voltage gain of 18 dB is demonstrated. The circuit achieves a sensitivity as low as −62 dBm and a power consumption of only 528 nW, with a total area of 634 × 391 μm2. Secondly, so as to reduce the area of the circuit, a design of a tuned-RF WuR with integrated current-reuse active inductor is presented. In this case, the WuR features a sensitivity of −55 dBm with a power consumption of 43.5 μW and a total area of 272 × 464 μm2, obtaining a significant area reduction at the expense of higher power consumption. The alternatives presented show a very low die footprint with a performance in line with most of the state-of-the-art contributions, making the topologies attractive in scenarios where high integrability and low cost-per-node are necessary.

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