scholarly journals Improving Generalized Discrete Fourier Transform (GDFT) Filter Banks with Low-Complexity and Reconfigurable Hybrid Algorithm

Digital ◽  
2020 ◽  
Vol 1 (1) ◽  
pp. 1-17
Author(s):  
Temidayo Otunniyi ◽  
Hermanus Myburgh
Keyword(s):  
Fourier Transform ◽  
Integrated Circuits ◽  
Power Consumption ◽  
Discrete Fourier Transform ◽  
High Speed ◽  
Filter Bank ◽  
Filter Design ◽  
Low Complexity ◽  
Lookup Table ◽  
Research Attention

With ever-increasing wireless network demands, low-complexity reconfigurable filter design is expected to continue to require research attention. Extracting and reconfiguring channels of choice from multi-standard receivers using a generalized discrete Fourier transform filter bank (GDFT-FB) is computationally intensive. In this work, a lower compexity algorithm is written for this transform. The design employs two different approaches: hybridization of the generalized discrete Fourier transform filter bank with frequency response masking and coefficient decimation method 1; and the improvement and implementation of the hybrid generalized discrete Fourier transform using a parallel distributed arithmetic-based residual number system (PDA-RNS) filter. The design is evaluated using MATLAB 2020a. Synthesis of area, resource utilization, delay, and power consumption was done on a Quartus 11 Altera 90 using the very high-speed integrated circuits (VHSIC) hardware description language. During MATLAB simulations, the proposed HGDFT algorithm attained a 66% reduction, in terms of number of multipliers, compared with existing algorithms. From co-simulation on the Quartus 11 Altera 90, optimization of the filter with PDA-RNS resulted in a 77% reduction in the number of occupied lookup table (LUT) slices, an 83% reduction in power consumption, and an 11% reduction in execution time, when compared with existing methods.

scholarly journals Low Complexity Non Maximally Coefficient Symmetry Multi Rate Filter Bank for Wideband Channelization

2021 ◽  
Author(s):  
Kirti Samir Vaidya ◽  
Dethe C.G ◽  
S. G. Akojwar
Keyword(s):  
Wireless Communication ◽  
Power Consumption ◽  
Input Signal ◽  
Filter Bank ◽  
Software Radio ◽  
Low Complexity ◽  
Polyphase Filter ◽  
The Individual ◽  
Hardware Efficiency ◽  
Communication Standard

Abstract For extracting the individual channels from input signal of wideband, Software Radio Channelizer was often used on multi-standard wireless communication. Despite the effective channelizer design that decreases the complexity of computational, delay and power consumption is challenging. Thus, to promote the effectiveness of the channelizer, we have provided the Non-Maximally Coefficient Symmetry Multirate Filter Bank. For this, a sharp wideband channelizer is designed to be using the latest class of masking responses with Non-maximally Decimated Polyphase Filter. Moreover, coefficient symmetry is incorporated into the Non-Maximally Coefficient Symmetry Multirate Filter Bank to improve the hardware efficiency and functionality of the proposed schemes. To prove the complexity enhancement of the proposed system, the design is analyzed with communication standard with existing methods.

scholarly journals High-speed programmable photonic circuits in a cryogenically compatible, visible–near-infrared 200 mm CMOS architecture

2021 ◽  
Author(s):  
Mark Dong ◽  
Genevieve Clark ◽  
Andrew J. Leenheer ◽  
Matthew Zimmermann ◽  
Daniel Dominguez ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
High Speed ◽  
Large Scale ◽  
Near Infrared ◽  
Response Times ◽  
Photonic Integrated Circuits ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Shifters ◽  
Oxide Semiconductor

AbstractRecent advances in photonic integrated circuits have enabled a new generation of programmable Mach–Zehnder meshes (MZMs) realized by using cascaded Mach–Zehnder interferometers capable of universal linear-optical transformations on N input/output optical modes. MZMs serve critical functions in photonic quantum information processing, quantum-enhanced sensor networks, machine learning and other applications. However, MZM implementations reported to date rely on thermo-optic phase shifters, which limit applications due to slow response times and high power consumption. Here we introduce a large-scale MZM platform made in a 200 mm complementary metal–oxide–semiconductor foundry, which uses aluminium nitride piezo-optomechanical actuators coupled to silicon nitride waveguides, enabling low-loss propagation with phase modulation at greater than 100 MHz in the visible–near-infrared wavelengths. Moreover, the vanishingly low hold-power consumption of the piezo-actuators enables these photonic integrated circuits to operate at cryogenic temperatures, paving the way for a fully integrated device architecture for a range of quantum applications.

Design of High-Speed Desensitized FIR Filter Employing Reduced Complexity SQRT Carry Select Adder

2019 ◽  
Vol 8 (10) ◽  
pp. 4288-4296
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Filter Design ◽  
Fir Filter ◽  
Simulation Tools ◽  
Booth Multiplier ◽  
Ripple Carry Adder ◽  
Carry Select Adder ◽  
Reduced Complexity ◽  
Fir Filter Design

In this research, a highly efficient desensitized FIR filter is designed to enhance the performance of digital filtering operation. With regard to FIR filter design, Multiplication and Accumulation component (MAC) forms the core processing entity. Half-band filters employing Ripple Carry Adder (RCA) based MAC structures have a sizeable number of logical elements, leading to high delay and high power consumption. To minimize these issues, a modified Booth multiplier encompassing SQRT Carry Select Adder (CSLA) based MAC component is proposed for the desensitized filter with reduced coefficients and employing lesser number of logical elements forgiving optimum performance with respect to delay and power consumption. The suggested FIR filter is simulated and assessed using EDA simulation tools from Modelsim 6.3c and Xilinx ISE. The results obtained from the proposed Desensitized FIR filter employing the modified booth multiplier with reduced complexity based SQRT CSLA show encouraging signs with respect to 12.08% reduction in delay and 2.2% reduction in power consumption when compared with traditional RCA based digital FIR filter.

Design of multi-carrier transceivers based on modified discrete fourier transform filter bank

2013 ◽  
Vol 33 (12) ◽  
pp. 3465-3468 ◽  
Author(s):  
Xiang JI ◽  
Ling ZHUANG ◽  
Kai SHAO ◽  
Guangyu WANG
Keyword(s):  
Fourier Transform ◽  
Discrete Fourier Transform ◽  
Filter Bank

High Throughput Realization of a New Systolic Array based FFT using CORDIC

2012 ◽  
Vol 2 (2) ◽  
pp. 53-59
Author(s):  
Gourav Jain ◽  
Shaik Rafi Ahamed
Keyword(s):  
Fourier Transform ◽  
Discrete Fourier Transform ◽  
High Throughput ◽  
Systolic Array ◽  
Digital Computer ◽  
High Speed ◽  
Clock Cycle ◽  
Complex Multiplication ◽  
Computer Complex ◽  
Dsp Applications

In this paper, the authors propose a new systolic array for radix-2, N-point discrete Fourier Transform (DFT) computation based on CORDIC (CO-ordinate Rotation Digital Computer). Complex multiplication can be done by this in a rather simple and elegant way. A CORDIC based multiplier less DFT architecture is designed in order to improve the performance of the system. It is able to provide two transforms per each clock cycle. The proposed design is well suited for high speed DSP-applications.

scholarly journals Power Efficient Clock Distribuition for Switched Capacitor DC-DC Converters

2018 ◽  
Vol 10 (1) ◽  
pp. 27
Author(s):  
A. S. R. Murthy ◽  
Sridhar T.
Keyword(s):  
Integrated Circuits ◽  
Power Consumption ◽  
Power Distribution ◽  
High Speed ◽  
Low Voltage ◽  
Data Communication ◽  
Distribution Networks ◽  
Propagation Delay ◽  
Switched Capacitor ◽  
Power Efficient

<p>In various VLSI based digital systems, on-chip interconnects have become the system bottleneck in state-of-the-art chips, limiting the performance of high-speed clock distributions and data communication devices in terms of propagation delay and power consumption. Increasing power requirements and power distribution to multi-core architectures is also posing a challenge to power distribution networks in the integrated circuits. Clock distribution networks for the switched capacitor converters becomes a non-trivial task and the increased interconnect lengths cause clock degradation and power dissipation. Therefore, this paper introduce low swing signaling schemes to decrease delay and power consumption. A comparative study presented of low voltage signaling schemes in terms of delay, power consumption and power delay product. Here, we have presented a power efficient signaling topology for driving the clocks to higher interconnect lengths.</p>

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