scholarly journals Design of New Au–NiCo MEMS Vertical Probe for Fine-Pitch Wafer-Level Probing

Crystals ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 485
Author(s):  
Xuan Luc Le ◽  
Sung-Hoon Choa
Keyword(s):  
Contact Stress ◽  
Carrying Capacity ◽  
Deformation Behavior ◽  
Solder Ball ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Stress And Deformation ◽  
Vertical Probe

As fine-pitch 3D wafer-level packaging becomes more popular in semiconductor industries, wafer-level prebond testing of various interconnect structures has become increasingly challenging. Additionally, improving the current-carrying capacity (CCC) and minimizing damage to the probe and micro-interconnect structures are very important issues in wafer-level testing. In this study, we propose an Au–NiCo MEMS vertical probe with an enhanced CCC to efficiently reduce the damage to the probe and various interconnect structures, including a solder ball, Cu pillar microbump, and TSV. The Au–NiCo probe has an Au layer inside the NiCo and an Au layer outside the surface of the NiCo probe to reduce resistivity and contact stress. The current-carrying capacity, contact stress, and deformation behavior of the probe and various interconnect structures were evaluated using numerical analyses. The Au–NiCo probe had a 150% higher CCC than the conventional NiCo probe. The maximum allowable current capacity of the 5000 µm-long Au–NiCo probe was 750 mA. The Au–NiCo probe exhibited less contact force and stress than the NiCo probe. The Au–NiCo probe also produced less deformation of various interconnect structures. These results indicate that the proposed Au–NiCo probe will be a prospective candidate for advanced wafer-level testing, with better probing efficiency and higher test yield and reliability than the conventional vertical probe.

Deformation Behavior of Various Interconnection Structures Using Fine Pitch Microelectromechanical Systems (MEMS) Vertical Probe

2021 ◽  
Vol 21 (5) ◽  
pp. 2949-2958
Author(s):  
Xuan Luc Le ◽  
Han Eul Lee ◽  
Sung-Hoon Choa
Keyword(s):  
Deformation Behavior ◽  
Solder Ball ◽  
Microelectromechanical Systems ◽  
Wafer Level ◽  
Silicon Oxide Layer ◽  
Cu Pillar ◽  
Fine Pitch ◽  
Cu Pillar Bump ◽  
Vertical Probe ◽  
Interconnection Structure

Recently, fine pitch wafer level packaging (WLP) technologies have drawn a great attention in the semiconductor industries. WLP technology uses various interconnection structures including microbumps and through-silicon-vias (TSVs). To increase yield and reduce cost, there is an increasing demand for wafer level testing. Contact behavior between probe and interconnection structure is a very important factor affecting the reliability and performance of wafer testing. In this study, with a MEMS vertical probe, we performed systematic numerical analysis of the deformation behavior of various interconnection structures, including solder bump, copper (Cu) pillar bump, solder capper Cu bump, and TSV. During probing, the solder ball showed the largest deformation. The Cu pillar bump also exhibited relatively large deformation. The Cu bump began to deform at OD of 10 μm. At OD of 20 μm, bump pillar was compressed, and the height of the bump decreased by 8.3%. The deformation behavior of the solder capped Cu bump was similar to that of the solder ball. At OD of 20 μm, the solder and Cu bumps were largely deformed, and the total height was reduced by 11%. The TSV structure showed the lowest deformation, but exerted the largest stress on the probe. In particular, copper protrusion at the outer edge of the via was observed, and very large shear stress was generated between the via and the silicon oxide layer. In summary, when probing various interconnection structures, the probe stress is less than that when using an aluminum pad. On the other hand, deformation of the structure is a critical issue. In order to minimize damage to the interconnection structure, smaller size probes or less overdrive should be used. This study will provide important guidelines for performing wafer-level testing and minimizing damage of probes and interconnection structures.

Challenges and approaches of ultra-fine pitch Cu pillar assembly on organic substrate using wafer level underfill

2013 ◽  
Author(s):  
Sharon Pei-Siang Lim ◽  
Li Yan Siow ◽  
Tai Chong Chai ◽  
Vempati Srinivasa Rao ◽  
Kohei Takeda ◽  
...  
Keyword(s):  
Organic Substrate ◽  
Wafer Level ◽  
Cu Pillar ◽  
Fine Pitch

Fine Pitch(40μm) Integration Platform for Flexible Hybrid Electronics using Fan-Out Wafer-level Packaging

2018 ◽  
Vol 2018 (1) ◽  
pp. 000064-000068
Author(s):  
Amir Hanna ◽  
Arsalan Alam ◽  
G. Ezhilarasu ◽  
Subramanian S. Iyer
Keyword(s):  
High Performance ◽  
Metal Films ◽  
Heterogeneous Integration ◽  
Wafer Level ◽  
Integration Platform ◽  
Wafer Level Packaging ◽  
Fine Pitch ◽  
Mechanical Bending

Abstract A flexible fan-out wafer-level packaging (FOWLP) process for heterogeneous integration of high performance dies in a flexible and biocompatible elastomeric package (FlexTrateTM) was used to assemble 625 dies with co-planarity and tilt <1μm, average die-shift of 3.28 μm with σ < 2.23 μm. Fine pitch interconnects (40μm pitch) were defined using a novel corrugated topography to mitigate the buckling phenomenon of metal films deposited on elastomeric substrates. Corrugated interconnects were then used to interconnect 200 dies, and then tested for cyclic mechanical bending reliability and have shown less than 7% change in resistance after bending down to 1 mm radius for 1,000 cycles.

Wafer Level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30μm

2011 ◽  
Vol 2011 (1) ◽  
pp. 000953-000960 ◽  
Author(s):  
Thomas Oppert ◽  
Rainer Dohle ◽  
Jörg Franke ◽  
Stefan Härter
Keyword(s):  
Solder Ball ◽  
Flip Chip ◽  
Temperature Cycling ◽  
Solder Paste ◽  
Wafer Level ◽  
Solder Alloys ◽  
Flip Chips ◽  
Fine Pitch ◽  
Solder Bumps ◽  
Cost Efficient

The most important technology driver in the electronics industry is miniaturization mainly driven by size reduction on wafer level and cost. One of the interconnection technologies for fine pitch applications with the potential for highest integration and cost savings is Flip Chip technology. The commonly used method of generating fine pitch solder bumps is by electroplating the solder. This process is difficult to control or even impossible if it comes to ternary or quaternary alloys. The work described in this study addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping and the use of a very large variety of solder alloys. This flexibility in the selection of the solder materials and UBM stacks is a large advantage if it is essential to improve temperature cycling resistance, drop test resistance, or to increase electromigration lifetime. The technology allows rapid changeover between different low melting solder alloys. Tighter bump pitches and a better bump quality (no flux entrapment) are achievable than with screen printing of solder paste. Because no solder material is wasted, the material costs for precious metal alloys like Au80Sn20 are much lower than with other bumping processes. Solder bumps with a diameter between to date 30 μm and 500 μm as well as small and large batches can be manufactured with one cost efficient process. To explore this potential, cost-efficient solder bumping and automated assembly technologies for the processing of Flip Chips have been developed and qualified. Flip Chips used in this study are 10 mm by 10 mm in size, have a pitch of 100 μm and a solder ball diameter of 30 μm, 40 μm or 50μm, respectively. Wafer level solder application has been done using wafer level solder sphere transfer process or solder sphere jetting technology, respectively. The latter tool has been used for many years in the wafer level packaging industry for both Flip Chip and chip scale packaging applications. It is commonly known in the industry as a solder ball bumping equipment. For the described work the process was scaled down for processing solder spheres with a diameter of 30 μm what was never done before that way worldwide. The research has shown that the underfill process is one of the most crucial factors when it comes to Flip Chip miniaturization for high reliability applications. Therefore, high performance underfill material was qualified initially [1]. Final long term reliability testing has been done according to MIL-STD883G, method 1010.8, condition B up to thirteen thousand cycles with excellent performance of the highly miniaturized solder joints. SEM/EDX and other analysis techniques will be presented. Additionally, an analysis of the failure mechanism will be given and recommendations for key applications and further miniaturization will be outlined.

Fine-Pitch RDL Integration for Fan-Out Wafer-Level Packaging

2020 ◽  
Author(s):  
Prayudi Lianto ◽  
Chin Wei Tan ◽  
Qi Jie Peng ◽  
Abdul Hakim Jumat ◽  
Xundong Dai ◽  
...  
Keyword(s):  
Wafer Level ◽  
Wafer Level Packaging ◽  
Fine Pitch
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