scholarly journals Prediction of a Two-Transistor Vertical QNOT Gate

2020 ◽  
Vol 10 (21) ◽  
pp. 7597
Author(s):  
Heesung Han ◽  
Chang-Hyun Kim
Keyword(s):  
Finite Element ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Circuits ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Inverter ◽  
Material Parameters ◽  
Element Simulation ◽  
Charge Injection Barrier ◽  
Injection Barrier

A new design of quaternary inverter (QNOT gate) is proposed by means of finite-element simulation. Traditionally, increasing the number of data levels in digital logic circuits was achieved by increasing the number of transistors. Our QNOT gate consists of only two transistors, resembling the binary complementary metal-oxide-semiconductor (CMOS) inverter, yet the two additional levels are generated by controlling the charge-injection barrier and electrode overlap. Furthermore, these two transistors are stacked vertically, meaning that the entire footprint only consumes the area of one single transistor. We explore several key geometrical and material parameters in a series of simulations to show how to systematically modulate and optimize the quaternary logic behaviors.

scholarly journals Fault Modeling of Graphene Nanoribbon FET Logic Circuits

Electronics ◽  
2019 ◽  
Vol 8 (8) ◽  
pp. 851 ◽  
Author(s):  
Gil-Tomàs ◽  
Gracia-Morán ◽  
Saiz-Adalid ◽  
Gil-Vicente
Keyword(s):  
Field Effect Transistor ◽  
Fault Tolerant ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Circuits ◽  
Graphene Nanoribbon ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Fault Models ◽  
New Materials ◽  
Effect Transistor

Due to the increasing defect rates in highly scaled complementary metal–oxide–semiconductor (CMOS) devices, and the emergence of alternative nanotechnology devices, reliability challenges are of growing importance. Understanding and controlling the fault mechanisms associated with new materials and structures for both transistors and interconnection is a key issue in novel nanodevices. The graphene nanoribbon field-effect transistor (GNR FET) has revealed itself as a promising technology to design emerging research logic circuits, because of its outstanding potential speed and power properties. This work presents a study of fault causes, mechanisms, and models at the device level, as well as their impact on logic circuits based on GNR FETs. From a literature review of fault causes and mechanisms, fault propagation was analyzed, and fault models were derived for device and logic circuit levels. This study may be helpful for the prevention of faults in the design process of graphene nanodevices. In addition, it can help in the design and evaluation of defect- and fault-tolerant nanoarchitectures based on graphene circuits. Results are compared with other emerging devices, such as carbon nanotube (CNT) FET and nanowire (NW) FET.

Electromechanical Computing at 500°C with Silicon Carbide

Science ◽  
2010 ◽  
Vol 329 (5997) ◽  
pp. 1316-1318 ◽  
Author(s):  
Te-Hao Lee ◽  
Swarup Bhunia ◽  
Mehran Mehregany
Keyword(s):  
Silicon Carbide ◽  
Thermal Management ◽  
High Performance ◽  
Field Effect Transistors ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Circuits ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Propulsion Systems ◽  
Heat Sinking

Logic circuits capable of operating at high temperatures can alleviate expensive heat-sinking and thermal-management requirements of modern electronics and are enabling for advanced propulsion systems. Replacing existing complementary metal-oxide semiconductor field-effect transistors with silicon carbide (SiC) nanoelectromechanical system (NEMS) switches is a promising approach for low-power, high-performance logic operation at temperatures higher than 300°C, beyond the capability of conventional silicon technology. These switches are capable of achieving virtually zero off-state current, microwave operating frequencies, radiation hardness, and nanoscale dimensions. Here, we report a microfabricated electromechanical inverter with SiC complementary NEMS switches capable of operating at 500°C with ultralow leakage current.

scholarly journals Design and Characteristics of CMOS Inverter based on Multisim and Cadence

2021 ◽  
Vol 2108 (1) ◽  
pp. 012034
Author(s):  
Haoran Xu ◽  
Jianghua Ding ◽  
Jian Dang
Keyword(s):  
Metal Oxide ◽  
Analog Circuits ◽  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Data Converters ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Inverter ◽  
And Performance

Abstract Known as complementary symmetrical metal oxide semiconductor (cos-mos), complementary metal oxide semiconductor is a metal oxide semiconductor field effect transistor (MOSFET) manufacturing process, which uses complementary and symmetrical pairs of p-type and n-type MOSFETs to realize logic functions. CMOS technology is used to build integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS) and other digital logic circuits. CMOS technology is also used in analog circuits, such as image sensors (CMOS sensors), data converters, RF circuits (RF CMOS), and highly integrated transceivers for various types of communications. Based on multisim 14.0 and cadence, the characteristics and performance of CMOS inverter are studied by simulation.

Organic CMOS Technology Based on Interface Doped Pentacene

2005 ◽  
Vol 871 ◽  
Author(s):  
Marcus Ahles ◽  
Roland Schmechel ◽  
Heinz von Seggern
Keyword(s):  
Gate Voltage ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Inverter ◽  
Organic Systems ◽  
Electron Accumulation ◽  
P Type

AbstractAn organic complementary-metal-oxide-semiconductor (CMOS) inverter based on pentacene acting as both n- and p-type organic semiconductor is presented. The circuit consists of two spatially separated transistors which are realized within one continuous pentacene layer. Both transistors act exclusively in unipolar mode with electron and hole mobilities of 0.11 cm2V-1s-1 and 0.10 cm2V-1s-1, respectively. In the domain of the n-channel, electron accumulation in the pentacene is enabled by deposition of traces of calcium acting as electron donator. The CMOS inverter works reliably within the range of the supply voltage (60 V) with a gain in between 17 and 24 which is among the highest values observed in organic systems. Nevertheless, the circuit shows hysteresis, which is explained by a gate voltage depending trap occupation in the n-channel.

A Review of QCA Nanotechnology as an Alternate to CMOS

2021 ◽  
Vol 17 ◽  
Author(s):  
Syed Farah Naz ◽  
Sadat Riyaz ◽  
Vijay Kumar Sharma
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Full Adder ◽  
Cmos Technology ◽  
Logic Circuits ◽  
Extensive Study ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Data Movement ◽  
Mos Device

Background: The human ken and understanding about esoteric phenomenon develops the period from space to the sub-atomic level. The passion to further explore the unexplored domains and dimensions boosts the human advancement in a cyclic way. A significant part of such passion follows in the electronics industry. Moore’s law is reaching the practical limitations because of further scaling of metal oxide semiconductor (MOS) devices. The need of a more dexterous and effective technology approach is demanded. Quantum-dot cellular automata (QCA) is an emerging technology which avoids the physical limitations of the MOS device. QCA is a dynamic computational transistor paradigm that addresses device density, power, operating frequency and interconnection problems. It requires an extensive study to know the fundamentals of logic implementation. Objective: Immense research and experiments due same vigor led to the evolving nanotechnology and a feasible alternative to complementary metal oxide semiconductor (CMOS) technology. A comprehensive study is presented in the paper to enhance the basics of QCA technology and the way of implementation of the logic circuits. Different existing circuits using QCA technology are discussed and compared for different parameters. Methods: Scaling the devices can reduce the power consumption of the MOS device. Quantum dots are nanostructures made from semi-conductive conventional materials. It is possible to model these constructions as 3-dimensional (3D) quantum energy wells. Logical operations and data movement are performed using Columbic interaction between nearby QCA cells instead of current flow. Results: The focus of this review paper is to study the trends which have been proposed and compared the designs for various digital circuits. The performance of different circuits such as XOR, adder, reversible gates and flip-flops are provided. Different logic circuits are compared on the parameters such as cell count, area and latency. At least 10 QCA cells are used for the XOR gate with 1 clock latency. Minimum 44 QCA cells are required to make a full adder with 1.25 clock latency.

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