A hybrid magnetic/complementary metal oxide semiconductor process design kit for the design of low-power non-volatile logic circuits

2012 ◽  
Vol 111 (7) ◽  
pp. 07E350 ◽  
Author(s):  
G. Di Pendina ◽  
G. Prenat ◽  
B. Dieny ◽  
K. Torki
Keyword(s):  
Metal Oxide ◽  
Low Power ◽  
Process Design ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Circuits ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Semiconductor Process

A 0.5 V Low-Power All-Digital Phase-Locked Loop in 65 nm Complementary Metal-Oxide-Semiconductor Process

2019 ◽  
Vol 15 (1) ◽  
pp. 64-75
Author(s):  
Fredrick Angelo R. Galapon ◽  
Mark Allen D. C. Agaton ◽  
Arcel G. Leynes ◽  
Lemuel Neil M. Noveno ◽  
Anastacia B. Alvarez ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Low Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Locked Loop ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Digital Phase ◽  
Semiconductor Process

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Low Power ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
State Dependency ◽  
Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

A Complementary Metal Oxide Semiconductor Process-Compatible Ferroelectric Tunnel Junction

2017 ◽  
Vol 9 (15) ◽  
pp. 13262-13268 ◽  
Author(s):  
Fabian Ambriz-Vargas ◽  
Gitanjali Kolhatkar ◽  
Maxime Broyer ◽  
Azza Hadj-Youssef ◽  
Rafik Nouar ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Ferroelectric Tunnel Junction ◽  
Semiconductor Process

Magnetotransistors sensitive to a magnetic field applied in two different directions

1991 ◽  
Vol 69 (3-4) ◽  
pp. 170-173
Author(s):  
M. Doan ◽  
Lj. Ristic
Keyword(s):  
Magnetic Field ◽  
Metal Oxide ◽  
Basic Principle ◽  
Magnetic Induction ◽  
Linear Response ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Base Region ◽  
Semiconductor Process

A lateral magnetotransistor that is sensitive to a magnetic field applied either parallel or perpendicular to the chip's surface is reported. It is fabricated using the standard complementary metal oxide semiconductor process. The deflection of the carriers in the base region is considered as the basic principle of operation. The device shows a linear response to a magnetic field in both directions. The minimum magnetic induction to be detected is in the order of 10 μT at f = 1 kHz.

Formation of cobalt silicide spikes in 0.18 μm complementary metal oxide semiconductor process

2001 ◽  
Vol 78 (20) ◽  
pp. 3091-3093 ◽  
Author(s):  
J. Y. Dai ◽  
Z. R. Guo ◽  
S. F. Tee ◽  
C. L. Tay ◽  
Eddie Er ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cobalt Silicide ◽  
Semiconductor Process
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