Modeling of tunnel field effect transistor: the impact of construction parameters

2016 ◽  
Author(s):  
Piotr Wiśniewski ◽  
Bogdan Majkusiak
2020 ◽  
Vol 10 (9) ◽  
pp. 3054
Author(s):  
Hyun Woo Kim ◽  
Daewoong Kwon

Tunnel field-effect transistor (Tunnel FET) with asymmetric spacer is proposed to obtain high on-current and reduced inverter delay simultaneously. In order to analyze the proposed Tunnel FET, electrical characteristics are evaluated by technology computer-aided design (TCAD) simulations with calibrated tunneling model parameters. The impact of the spacer κ values on tunneling rate is investigated with the symmetric spacer. As the κ values of the spacer increase, the on-current becomes enhanced since tunneling probabilities are increased by the fringing field through the spacer. However, on the drain-side, that fringing field through the drain-side spacer increases ambipolar current and gate-to-drain capacitance, which degrades leakage property and switching response. Therefore, the drain-side low-κ spacer, which makes the low fringing field, is adapted asymmetrically with the source-side high-κ spacer. This asymmetric spacer results in the reduction of gate-to-drain capacitance and switching delay with the improved on-current induced by the source-side high-κ spacer.


2021 ◽  
Author(s):  
PRABHAT SINGH ◽  
DHARMENDRA SINGH YADAV

Abstract In this proposed work, a novel single gate F-shaped channel tunnel field effect transistor (SG-FC-TFET) is proposed and investigated. The impact of thickness of the source region and lateral tunneling length between the gate oxide and edge of the source region on analog and radio frequency parameters are investigated with appropriate source and drain lateral length through the 2D-TCAD tool. The slender shape of the source enhanced the electric le crowding effect at the corners of the source region which reflect in term of high On-current (Ion). The Ion of proposed device is increased up to 10-4 A=μm with reduced sub-threshold swing (SS) is 7.3 mV/decade and minimum turn-ON voltage (Von = 0.28 V). The analog/RF parameters of SG-FC-TFET are optimized.


2010 ◽  
Vol E93-C (5) ◽  
pp. 540-545 ◽  
Author(s):  
Dong Seup LEE ◽  
Hong-Seon YANG ◽  
Kwon-Chil KANG ◽  
Joung-Eob LEE ◽  
Jung Han LEE ◽  
...  

2021 ◽  
Vol 16 (1) ◽  
Author(s):  
Xiaoshi Jin ◽  
Yicheng Wang ◽  
Kailu Ma ◽  
Meile Wu ◽  
Xi Liu ◽  
...  

AbstractA bilateral gate-controlled S/D symmetric and interchangeable bidirectional tunnel field effect transistor (B-TFET) is proposed in this paper, which shows the advantage of bidirectional switching characteristics and compatibility with CMOS integrated circuits compared to the conventional asymmetrical TFET. The effects of the structural parameters, e.g., the doping concentrations of the N+ region and P+ region, length of the N+ region and length of the intrinsic region, on the device performances, e.g., the transfer characteristics, Ion–Ioff ratio and subthreshold swing, and the internal mechanism are discussed and explained in detail.


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