The Impact of Fringing Field on the Device Performance of a p-Channel Tunnel Field-Effect Transistor With a High-$\kappa$ Gate Dielectric

2012 ◽  
Vol 59 (2) ◽  
pp. 277-282 ◽  
Author(s):  
Abhijit Mallik ◽  
Avik Chattopadhyay
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Gate Dielectric ◽  
Device Performance ◽  
Fringing Field ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
The Impact

scholarly journals Analysis on Tunnel Field-Effect Transistor with Asymmetric Spacer

2020 ◽  
Vol 10 (9) ◽  
pp. 3054
Author(s):  
Hyun Woo Kim ◽  
Daewoong Kwon
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Model Parameters ◽  
Tunnel Fet ◽  
Drain Side ◽  
Fringing Field ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
The Impact

Tunnel field-effect transistor (Tunnel FET) with asymmetric spacer is proposed to obtain high on-current and reduced inverter delay simultaneously. In order to analyze the proposed Tunnel FET, electrical characteristics are evaluated by technology computer-aided design (TCAD) simulations with calibrated tunneling model parameters. The impact of the spacer κ values on tunneling rate is investigated with the symmetric spacer. As the κ values of the spacer increase, the on-current becomes enhanced since tunneling probabilities are increased by the fringing field through the spacer. However, on the drain-side, that fringing field through the drain-side spacer increases ambipolar current and gate-to-drain capacitance, which degrades leakage property and switching response. Therefore, the drain-side low-κ spacer, which makes the low fringing field, is adapted asymmetrically with the source-side high-κ spacer. This asymmetric spacer results in the reduction of gate-to-drain capacitance and switching delay with the improved on-current induced by the source-side high-κ spacer.

Optimal design for a high performance H-JLTFET using HfO2 as a gate dielectric for ultra low power applications

RSC Advances ◽  
2014 ◽  
Vol 4 (43) ◽  
pp. 22803-22807 ◽  
Author(s):  
Pranav Kumar Asthana ◽  
Bahniman Ghosh ◽  
Shiromani Bal Mukund Rahi ◽  
Yogesh Goswami
Keyword(s):  
Optimal Design ◽  
Low Power ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Gate Dielectric ◽  
Ultra Low Power ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

In this paper we have proposed an optimal design for a hetero-junctionless tunnel field effect transistor using HfO2 as a gate dielectric.

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