scholarly journals Image Sensing Technology. A CMOS High-Speed Non-Destructive Intermediate Image Sensor.

2001 ◽  
Vol 55 (2) ◽  
pp. 264-270
Author(s):  
Dwi Handoko ◽  
Shoji Kawahito ◽  
Yoshiaki Tadokoro ◽  
Akira Matsuzawa
Keyword(s):  
High Speed ◽  
Image Sensor ◽  
Image Sensing ◽  
Sensing Technology ◽  
Intermediate Image ◽  
Non Destructive

scholarly journals Image Sensing Technology. A Smart Image Sensor with Quad-Tree Scan.

2001 ◽  
Vol 55 (2) ◽  
pp. 287-292
Author(s):  
Tomohiro Nezuka ◽  
Junichi Akita ◽  
Makoto Ikeda ◽  
Kunihiro Asada
Keyword(s):  
Image Sensor ◽  
Image Sensing ◽  
Quad Tree ◽  
Sensing Technology

A CMOS Image Sensor with Non-Destructive High-Speed Imaging Mode and Its Applications

2000 ◽  
Vol 12 (5) ◽  
pp. 502-507
Author(s):  
Dwi Handoko ◽  
◽  
Shoji Kawahito ◽  
Minoru Kumahara ◽  
Nobuhiro Kawai ◽  
...  
Keyword(s):  
Video Compression ◽  
High Speed ◽  
Motion Vector ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Moving Object ◽  
High Speed Imaging ◽  
Imaging Mode ◽  
Vector Estimation ◽  
Non Destructive

This paper describes a CMOS image sensor with non-destructive high-speed imaging mode. The proposed sensor reads out high-speed intermediate images without destroying accumulated signal charge and captures video-rate (30 frame/s) images with high SNR. The application of the sensor to a low power motion vector estimation for video compression and high-fidelity imaging of moving object with tracking are also presented. Motion vector estimation using the proposed sensor is possible to reduce computational power by a factor of 1/10 compared to the full search algorithm. The simulation results show that the proposed image sensor with nondestructive high-speed imaging mode is useful for moving object imaging with less shape distortion.

scholarly journals Image Sensing Technology. A CMOS Image Sensor with High Sensitivity and Low Dark Current.

2001 ◽  
Vol 55 (2) ◽  
pp. 257-263 ◽  
Author(s):  
Ikuko Inoue ◽  
Tetsuya Yamaguchi ◽  
Hidetoshi Nozaki ◽  
Ryouhei Miyagawa ◽  
Sohei Manabe
Keyword(s):  
Dark Current ◽  
High Sensitivity ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Image Sensing ◽  
Sensing Technology

scholarly journals Image Sensing Technology. A CMOS Image Sensor with a Simple FPN-Reduction Technology and a Hole Accumulated Diode.

2001 ◽  
Vol 55 (2) ◽  
pp. 252-256
Author(s):  
Kazuya Yonemoto ◽  
Hirofumi Sumi ◽  
Ryoji Suzuki ◽  
Takahisa Ueno ◽  
Keiji Mabuchi
Keyword(s):  
Cmos Image Sensor ◽  
Image Sensor ◽  
Image Sensing ◽  
Sensing Technology

scholarly journals Towards an Efficient CNN Inference Architecture Enabling In-Sensor Processing

Sensors ◽  
2021 ◽  
Vol 21 (6) ◽  
pp. 1955
Author(s):  
Md Jubaer Hossain Pantho ◽  
Pankaj Bhowmik ◽  
Christophe Bobda
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Image Sensor ◽  
Machine Learning Algorithms ◽  
Hierarchical Optimization ◽  
Computation Method ◽  
Optimization Approach ◽  
Efficient Computation ◽  
Feature Maps ◽  
Dynamic Power

The astounding development of optical sensing imaging technology, coupled with the impressive improvements in machine learning algorithms, has increased our ability to understand and extract information from scenic events. In most cases, Convolution neural networks (CNNs) are largely adopted to infer knowledge due to their surprising success in automation, surveillance, and many other application domains. However, the convolution operations’ overwhelming computation demand has somewhat limited their use in remote sensing edge devices. In these platforms, real-time processing remains a challenging task due to the tight constraints on resources and power. Here, the transfer and processing of non-relevant image pixels act as a bottleneck on the entire system. It is possible to overcome this bottleneck by exploiting the high bandwidth available at the sensor interface by designing a CNN inference architecture near the sensor. This paper presents an attention-based pixel processing architecture to facilitate the CNN inference near the image sensor. We propose an efficient computation method to reduce the dynamic power by decreasing the overall computation of the convolution operations. The proposed method reduces redundancies by using a hierarchical optimization approach. The approach minimizes power consumption for convolution operations by exploiting the Spatio-temporal redundancies found in the incoming feature maps and performs computations only on selected regions based on their relevance score. The proposed design addresses problems related to the mapping of computations onto an array of processing elements (PEs) and introduces a suitable network structure for communication. The PEs are highly optimized to provide low latency and power for CNN applications. While designing the model, we exploit the concepts of biological vision systems to reduce computation and energy. We prototype the model in a Virtex UltraScale+ FPGA and implement it in Application Specific Integrated Circuit (ASIC) using the TSMC 90nm technology library. The results suggest that the proposed architecture significantly reduces dynamic power consumption and achieves high-speed up surpassing existing embedded processors’ computational capabilities.

scholarly journals On-CMOS Image Sensor Processing for Lane Detection

Sensors ◽  
2021 ◽  
Vol 21 (11) ◽  
pp. 3713
Author(s):  
Soyeon Lee ◽  
Bohyeok Jeong ◽  
Keunyeol Park ◽  
Minkyu Song ◽  
Soo Youn Kim
Keyword(s):  
Edge Detection ◽  
High Speed ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Image Resolution ◽  
Lane Detection ◽  
Frame Rate ◽  
Total Power ◽  
Detection Accuracy ◽  
Total Power Consumption

This paper presents a CMOS image sensor (CIS) with built-in lane detection computing circuits for automotive applications. We propose on-CIS processing with an edge detection mask used in the readout circuit of the conventional CIS structure for high-speed lane detection. Furthermore, the edge detection mask can detect the edges of slanting lanes to improve accuracy. A prototype of the proposed CIS was fabricated using a 110 nm CIS process. It has an image resolution of 160 (H) × 120 (V) and a frame rate of 113, and it occupies an area of 5900 μm × 5240 μm. A comparison of its lane detection accuracy with that of existing edge detection algorithms shows that it achieves an acceptable accuracy. Moreover, the total power consumption of the proposed CIS is 9.7 mW at pixel, analog, and digital supply voltages of 3.3, 3.3, and 1.5 V, respectively.

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