scholarly journals A SINGLE-CHIP CMOS-MEMS MICROGRAVITY ACCELEROMETER

2012 ◽  
Author(s):  
Y. Zhang ◽  
G. Meng ◽  
N. Yazdi
Keyword(s):  
Single Chip ◽  
Cmos Mems

Single-Chip CMOS-MEMS Dual Mode Scanning Microwave Microscope

2013 ◽  
Vol 61 (12) ◽  
pp. 4621-4629 ◽  
Author(s):  
M. Azizi ◽  
N. Sarkar ◽  
R. R. Mansour
Keyword(s):  
Single Chip ◽  
Dual Mode ◽  
Microwave Microscope ◽  
Cmos Mems

Micromotors unit based on CMOS-MEMS technology integrated on a single chip

2021 ◽  
Author(s):  
Andrea Lopez-Tapia ◽  
Luis Sanchez-Marquez ◽  
Mario Alfredo Reyes-Barranca ◽  
Griselda Stephany Abarca-Jimenez ◽  
Luis Martin Flores-Nava
Keyword(s):  
Single Chip ◽  
Mems Technology ◽  
Cmos Mems

RF CMOS-MEMS Switch with Low-Voltage Operation for Single-Chip RF LSIs

2006 ◽  
Author(s):  
K. Kuwabara ◽  
N. Sato ◽  
T. Shimamura ◽  
H. Morimura ◽  
J. Kodate ◽  
...  
Keyword(s):  
Low Voltage ◽  
Rf Cmos ◽  
Single Chip ◽  
Mems Switch ◽  
Low Voltage Operation ◽  
Cmos Mems

Phase Locked Loop Integrated System

2010 ◽  
Vol 164 ◽  
pp. 221-226 ◽  
Author(s):  
J. Charlamov ◽  
R. Navickas
Keyword(s):  
Noise Analysis ◽  
Phase Locked Loop ◽  
Integrated System ◽  
Voltage Controlled Oscillator ◽  
Mems Devices ◽  
Single Chip ◽  
Fabrication Errors ◽  
Electromechanical Performance ◽  
Cmos Mems ◽  
A Charge

CMOS-MEMS integration is an indispensable technique for self-calibration of electromechanical performance to make MEMS devices independent on environmental drift or fabrication errors. The goal of single-chip integration (the “holy grail” for the semiconductor timing industry) would be to include the resonator, the oscillator, the PLL and a temperature compensation circuit (TCC) on a single silicon substrate. The current structure of silicon MEMS-based devices utilizes a stacked-die arrangement, housed in a multi-chip package [1]. MEMS-based timing circuits often use PLLs, which can succumb to phase jitter and noise at higher timing frequencies. The architecture of a charge pump phase locked loop (CPPLL) is proposed in this work. It is discussed how its functional blocks influence the overall system performance. We have performed voltage-controlled oscillator (VCO) phase noise analysis and have determined the relationship between CPPLL and VCO phase noises and have discussed the requirements and results of the accomplished design.

Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications

MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 19-27 ◽  
Author(s):  
Wei William Lee ◽  
Paul S. Ho
Keyword(s):  
Packing Density ◽  
Propagation Delay ◽  
Single Chip ◽  
Crosstalk Noise ◽  
Metal Line ◽  
Total Delay ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Interconnect Delay ◽  
Interconnect Technology

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

Research on highly parallel embedded control system design and implementation method

Impact ◽  
2019 ◽  
Vol 2019 (10) ◽  
pp. 44-46
Author(s):  
Masato Edahiro ◽  
Masaki Gondo
Keyword(s):  
Computer Architecture ◽  
Intelligent Systems ◽  
Large Scale ◽  
General Purpose ◽  
Heterogeneous Structure ◽  
Single Chip ◽  
Powertrain Control ◽  
Processing Power ◽  
Hardware Description ◽  
Many Core

The pace of technology's advancements is ever-increasing and intelligent systems, such as those found in robots and vehicles, have become larger and more complex. These intelligent systems have a heterogeneous structure, comprising a mixture of modules such as artificial intelligence (AI) and powertrain control modules that facilitate large-scale numerical calculation and real-time periodic processing functions. Information technology expert Professor Masato Edahiro, from the Graduate School of Informatics at the Nagoya University in Japan, explains that concurrent advances in semiconductor research have led to the miniaturisation of semiconductors, allowing a greater number of processors to be mounted on a single chip, increasing potential processing power. 'In addition to general-purpose processors such as CPUs, a mixture of multiple types of accelerators such as GPGPU and FPGA has evolved, producing a more complex and heterogeneous computer architecture,' he says. Edahiro and his partners have been working on the eMBP, a model-based parallelizer (MBP) that offers a mapping system as an efficient way of automatically generating parallel code for multi- and many-core systems. This ensures that once the hardware description is written, eMBP can bridge the gap between software and hardware to ensure that not only is an efficient ecosystem achieved for hardware vendors, but the need for different software vendors to adapt code for their particular platforms is also eliminated.

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