Modelling analysis and experiments of polycrystalline silicon directional solidification in an annular heating field

2017 ◽  
Vol 108 (12) ◽  
pp. 1055-1063
Author(s):  
Xuli Zhu ◽  
Long Xu ◽  
Jinmei Huang ◽  
Hongqiong Wu
Keyword(s):  
Directional Solidification ◽  
Polycrystalline Silicon ◽  
Modelling Analysis

Directional Solidification Behaviors of Polycrystalline Silicon by Electron-Beam Melting

2013 ◽  
Vol 52 (10S) ◽  
pp. 10MB09 ◽  
Author(s):  
Jun-Kyu Lee ◽  
Jin-Seok Lee ◽  
Bo-Yun Jang ◽  
Joon-Soo Kim ◽  
Young-Soo Ahn ◽  
...  
Keyword(s):  
Electron Beam ◽  
Directional Solidification ◽  
Electron Beam Melting ◽  
Polycrystalline Silicon

Effects of Geometrical Parameters in the DS Method for the Growth of Large Sized Polycrystal Silicon

2007 ◽  
Author(s):  
Jung-Hoon Hwang ◽  
Youn-Jea Kim ◽  
Joong-Won Shur ◽  
Dae-Ho Yoon
Keyword(s):  
Directional Solidification ◽  
Polycrystalline Silicon ◽  
Crystalline Silicon ◽  
Thermal Characteristics ◽  
Geometrical Parameters ◽  
Dynamics Model ◽  
Heat Transfer Characteristics ◽  
Short Cycle ◽  
Market Growth ◽  
Solidification Processes

Polycrystalline silicon (Si) wafers share more than 60% of the photovoltaic market due to its cost advantage compared to the mono-crystalline silicon wafers. Several solidification processes have been developed by industries, including casting, heat exchanger method and electromagnetic casting. However, the market growth using mono- and polycrystalline Si wafers might be saturated due to the shortage of Si feedstock. One of the methods to solve this issue is to make higher quality polycrystalline Si wafers which are capable of producing higher efficiency solar cells. In this work, the effects of changing several geometrical parameters were evaluated to improve the directional solidification (DS) method and to satisfy the above-mentioned main targets. The developed DS method has the advantages of the small heat loss, short cycle time and efficient directional solidification. Based on the fluid dynamics model, the numerical simulation was performed on the thermal characteristics during the DS process. Using a commercial CFD code, Fluent, the heat transfer characteristics in the DS system are calculated, and the results are graphically depicted.

Numerical Simulation of Thermal Distribution during the Directional Solidification of Polycrystalline Silicon Ingot

2019 ◽  
Vol 18 (1) ◽  
pp. 1043-1047
Author(s):  
Dan Wu ◽  
Weizhong Sun ◽  
Qiuyan Hao ◽  
Jianguo Zhao ◽  
Caichi Liu
Keyword(s):  
Numerical Simulation ◽  
Directional Solidification ◽  
Polycrystalline Silicon ◽  
Silicon Ingot ◽  
Thermal Distribution

Directional solidification of polycrystalline silicon ingots by successive relaxation of supercooling method

2007 ◽  
Vol 308 (1) ◽  
pp. 5-9 ◽  
Author(s):  
Koji Arafune ◽  
Eichiro Ohishi ◽  
Hitoshi Sai ◽  
Yoshio Ohshita ◽  
Masafumi Yamaguchi
Keyword(s):  
Directional Solidification ◽  
Polycrystalline Silicon ◽  
Successive Relaxation

Preparation of TEM samples by focused ion beams

1995 ◽  
Vol 53 ◽  
pp. 518-519
Author(s):  
John F. Walker ◽  
J C Reiner ◽  
C Solenthaler
Keyword(s):  
Integrated Circuit ◽  
Polycrystalline Silicon ◽  
Field Effect Transistor ◽  
High Spatial Resolution ◽  
Ion Beam ◽  
Ion Beams ◽  
Focused Ion Beams ◽  
Precise Location ◽  
Effect Transistor ◽  
Circuit Technology

The high spatial resolution available from TEM can be used with great advantage in the field of microelectronics to identify problems associated with the continually shrinking geometries of integrated circuit technology. In many cases the location of the problem can be the most problematic element of sample preparation. Focused ion beams (FIB) have previously been used to prepare TEM specimens, but not including using the ion beam imaging capabilities to locate a buried feature of interest. Here we describe how a defect has been located using the ability of a FIB to both mill a section and to search for a defect whose precise location is unknown. The defect is known from electrical leakage measurements to be a break in the gate oxide of a field effect transistor. The gate is a square of polycrystalline silicon, approximately 1μm×1μm, on a silicon dioxide barrier which is about 17nm thick. The break in the oxide can occur anywhere within that square and is expected to be less than 100nm in diameter.

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