scholarly journals ESTIMATION METHOD FOR SIMULTANEOUS SWITCHING NOISE IN POWER DELIVERY NETWORK FOR HIGH-SPEED DIGITAL SYSTEM DESIGN

2012 ◽  
Vol 125 ◽  
pp. 79-95 ◽  
Author(s):  
Tong-Hao Ding ◽  
Yu-Shan Li ◽  
Dong-Chu Jiang ◽  
Yong-Zhe Qu ◽  
Xu Yan
Keyword(s):  
System Design ◽  
High Speed ◽  
Estimation Method ◽  
Digital System ◽  
Power Delivery ◽  
Switching Noise ◽  
Power Delivery Network ◽  
Simultaneous Switching Noise ◽  
Digital System Design ◽  
Simultaneous Switching

High-Speed Digital System Design

2020 ◽  
Author(s):  
Anatoly Belous ◽  
Vitali Saladukha
Keyword(s):  
System Design ◽  
High Speed ◽  
Digital System ◽  
Digital System Design

scholarly journals Investigation and Analysis of the Simultaneous Switching Noise in Power Distribution Network with Multi-Power Supplies of High Speed CMOS Circuits

2017 ◽  
Vol 2017 ◽  
pp. 1-10 ◽  
Author(s):  
Khaoula Ait Belaid ◽  
Hassan Belahrach ◽  
Hassan Ayad
Keyword(s):  
Power Distribution ◽  
High Speed ◽  
Electromagnetic Coupling ◽  
Distribution Network ◽  
Switching Noise ◽  
Power Distribution Network ◽  
Vector Fitting ◽  
Rational Function Approximation ◽  
Simultaneous Switching Noise ◽  
Simultaneous Switching

The paper studies a simultaneous switching noise (SSN) in a power distribution network (PDN) with dual supply voltages and two cores. This is achieved by reducing the admittance matrix Y of the PDN then calculating frequency domain impedance with rational function approximation using vector fitting. This paper presents a method of computing the simultaneous switching noise through a switching current, whose properties and details are described. Thus, the results are discussed and performed using MATLAB and PSpice tools. It demonstrated that the presence of many cores in the same PCB influences the SSN due to electromagnetic coupling.

A NOVEL DESIGN METHODOLOGY FOR REDUCING SIMULTANEOUS SWITCHING NOISE EVALUATED BY A DIFFERENTIAL-IBIS STRUCTURE

2010 ◽  
Vol 19 (06) ◽  
pp. 1275-1297
Author(s):  
WEN-TZENG HUANG ◽  
SUN-YEN TAN ◽  
YUAN-JEN CHANG
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Low Voltage ◽  
Switching Noise ◽  
Decoupling Capacitors ◽  
Input Noise ◽  
Low Voltage Operation ◽  
Simultaneous Switching Noise ◽  
Simultaneous Switching ◽  
Ibis Model

Modern electronic products increasingly require high speed, high density, and low-voltage operation. In such designs, the power-delivery system could be affected by input noise to the point that it becomes unstable. Simultaneous switching noise (SSN) is a major factor that interferes with power integrity. Although decoupling capacitors cannot effectively alleviate the problem of SSN, they have been generally used in the HP Simulation Program with Integrated Circuit Emphasis model for reducing SSN. The differential I/O buffer information specification (D-IBIS) model uses equivalent circuits to describe the behavior of an integrated circuit. In this study, we propose a novel method for effectively reducing SSN evaluated by an enhanced D-IBIS model with decoupling capacitors and a high-frequency low-impendence circuit. We show that this new method reduces noise by about 40–64% compared to traditional design methodologies.

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