Thermal modeling technique for large complex isogrid structures

2002 ◽  
Author(s):  
J. Abbott ◽  
S.-C. Lee
Keyword(s):  
Thermal Modeling ◽  
Modeling Technique ◽  
Large Complex

Multi-Packaging-Level Thermal Modeling Technique for Silicon Chip Transistors

2009 ◽  
Author(s):  
Tohru Suwa ◽  
Hamid Hadim
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Heat Source ◽  
Thermal Modeling ◽  
Critical Issue ◽  
Modeling Technique ◽  
Superposition Method ◽  
Heat Sources ◽  
Element Analysis ◽  
Modeling And Analysis

Although thermal performance is always a critical issue in electronic packaging design at every packaging level, there is a significant lack of reliable and efficient thermal modeling and analysis techniques at the silicon chip level. With millions of transistor gates acting as heat sources, accurate thermal modeling and analysis at micrometer level has not been possible using conventional techniques. For the present study, an efficient and accurate multi-level thermal modeling and analysis technique integrating transistor level into silicon chip level has been developed. The technique combines finite element analysis sub-modeling and superposition methods for more efficient modeling and simulation. Detailed temperature distribution caused by a single heat source is obtained using the finite element sub-modeling technique, while the temperature rise distribution caused by multiple heat sources is obtained using the superposition method. Using the proposed thermal modeling methodology, one case of finite element analysis with a single heat source is sufficient for modeling a silicon chip with millions of transistors acting as heat sources. When the whole package is modeled in the finite element analysis, the effect of the package is also included in the superposition results, which makes possible to model over one million transistors in a silicon chip. No present methodologies for existing silicon chip thermal modeling techniques have been able to model such a large number of transistors. The capabilities of the proposed methodology are demonstrated through a case study involving thermal modeling and analysis of a microprocessor chip.

Thermal Modeling Technique for Multiple Transistors Within Silicon Chip

2011 ◽  
Vol 133 (4) ◽  
Author(s):  
Tohru Suwa ◽  
Hamid Hadim
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Heat Source ◽  
Hot Spots ◽  
Thermal Modeling ◽  
Modeling Technique ◽  
Heat Sources ◽  
Element Analysis ◽  
Modeling And Analysis ◽  
Silicon Chips

Although thermal performance is always a critical issue in electronic packaging design at every packaging level, there is a significant lack of reliable and efficient thermal modeling and analysis techniques at the silicon chip level. Sharp temperature increases within small areas, which are called “hot spots”, often occur in silicon chips. For more efficient designs, the temperature and location of hot spots need to be predicted with acceptable accuracy. With millions of transistor gates acting as heat sources, accurate thermal modeling and analysis of silicon chips at micrometer level has not been possible using conventional techniques. In the present study, an efficient and accurate multi-level thermal modeling and analysis technique has been developed. The technique combines finite element analysis sub-modeling and a superposition method for more efficient modeling and simulation. Detailed temperature distribution caused by a single heat source is obtained using the finite element sub-modeling technique, while the temperature rise distribution caused by multiple heat sources is obtained by superimposing the finite element analysis result. Using the proposed thermal modeling methodology, one case of finite element analysis with a single heat source is sufficient for modeling a silicon chip with millions of transistors acting as heat sources. When the whole package is modeled using the finite element method, the effect of the package and its boundary conditions are also included in the superposition results, which makes it possible to model a large number of transistors on a silicon chip. The capabilities of the proposed methodology are demonstrated through a case study involving thermal modeling and analysis of a microprocessor chip with 4 × 106 transistors.

THERMAL MODELING OF ICE-PACKS IN COOLING VESTS FOR EXTREME HOT CLIMATIC CONDITION: A NUMERICAL APPROACH

2018 ◽  
Author(s):  
Vedant Bhuyar ◽  
Shiv Ram Suthar ◽  
Mohit Vijay ◽  
Prodyut R. Chakraborty
Keyword(s):  
Climatic Condition ◽  
Thermal Modeling ◽  
Numerical Approach

Using the principles and approaches of flexible methodology (agile) in the planning and implementation of the educational process

2020 ◽  
pp. 48-55
Author(s):  
TING ZHU
Keyword(s):  
Labor Market ◽  
Program Development ◽  
Development Process ◽  
Project Manager ◽  
Educational Process ◽  
Large Complex ◽  
Complex Projects ◽  
Quality Risk ◽  
The Government

The educatonal program development process is challenging with many stakeholders: students, teachers, parents, administrators, employers, and the government. Each stakeholder has compettve priorites; Quality, risk, resources and costs limitaton. Large complex projects require the management of a skilled and experienced project manager. It is the preparaton of curricula for joint internatonal educatonal programs with the use of Agile tools and technologies. The main "customer" in this program is a student, and the ultmate goal of each project within the program-the competence of the student in the labor market afer receiving the diploma. Therefore, this program can be considered difcult, and it is constantly evolves, because the demands of the labor market of China is constantly changing and developing.

Ensemble RBF Modeling Technique for Quality Design

2019 ◽  
Author(s):  
Linhan Ouyang ◽  
Liangqi Wan ◽  
Chanseok Park ◽  
Jianjun Wang ◽  
Yizhong Ma
Keyword(s):  
Modeling Technique ◽  
Quality Design
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