All-Optical Performance Characterization of Silicon Mach–Zehnder Modulator for Wafer-Level Test

2019 ◽  
Author(s):  
Hiroshi Fukuda ◽  
Yoshiho Maeda ◽  
Toru Miura ◽  
Shinji Matsuo
Keyword(s):  
Optical Performance ◽  
Wafer Level ◽  
Performance Characterization ◽  
All Optical ◽  
Mach Zehnder Modulator

Optical performance characterization of AWG devices using low coherence interferometer

2002 ◽  
Author(s):  
Dongqing Cao ◽  
Ming Yan ◽  
Brian McGinnis ◽  
Tony J. Ticknor ◽  
Jane C. Lam ◽  
...  
Keyword(s):  
Optical Performance ◽  
Performance Characterization ◽  
Low Coherence

Optical performance characterization of light-logging actigraphy dosimeters

2017 ◽  
Vol 34 (4) ◽  
pp. 545 ◽  
Author(s):  
Luke L. A. Price ◽  
Andrey Lyachev ◽  
Marina Khazova
Keyword(s):  
Optical Performance ◽  
Performance Characterization

Characterization of Unfilled Tungsten Plugs on a 0.35μm CMOS Multilevel Metallization Process

1996 ◽  
Author(s):  
H. Sur ◽  
S. Bothra ◽  
Y. Strunk ◽  
J. Hahn
Keyword(s):  
Process Development ◽  
Process Integration ◽  
Wafer Level ◽  
Electrical Failure ◽  
Analysis Techniques ◽  
Integration Approach ◽  
Intermetal Dielectric ◽  
Metallization Process ◽  
Section Analysis

Abstract An investigation into metallization/interconnect failures during the process development phase of an advanced 0.35μm CMOS ASIC process is presented. The corresponding electrical failure signature was electrical shorting on SRAM test arrays and subsequently functional/Iddq failures on product-like test vehicles. Advanced wafer-level failure analysis techniques and equipment were used to isolate and identify the leakage source as shorting of metal lines due to tungsten (W) residue which was originating from unfilled vias. Further cross-section analysis revealed that the failing vias were all exposed to the intermetal dielectric spin-on glass (SOG) material used for filling the narrow spaces between metal lines. The outgassing of the SOG in the exposed regions of the via prior to and during the tungsten plug deposition is believed to be the cause of the unfilled vias. This analysis facilitated further process development in eliminating the failure mechanism and since then no failures of this nature have been observed. The process integration approach used to eliminate the failure is discussed.

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