A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices

2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) ◽

10.23919/date.2018.8342024 ◽

2018 ◽

Cited By ~ 1

Author(s):

Marcello Dalpasso ◽

Davide Bertozzi ◽

Michele Favalli

Keyword(s):

Digital Technologies ◽

Boolean Model ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing

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Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing

IEICE Transactions on Electronics ◽

10.1587/transele.e99.c.1219 ◽

2016 ◽

Vol E99.C (10) ◽

pp. 1219-1225

Author(s):

Masahiro ISHIDA ◽

Toru NAKURA ◽

Takashi KUSAKA ◽

Satoshi KOMATSU ◽

Kunihiro ASADA

Keyword(s):

Power Supply ◽

Supply Voltage ◽

Voltage Control ◽

Fault Testing ◽

Power Supply Voltage ◽

Delay Fault ◽

Delay Fault Testing

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Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs *

2020 IEEE 29th Asian Test Symposium (ATS) ◽

10.1109/ats49688.2020.9301568 ◽

2020 ◽

Author(s):

Shao-Chun Hung ◽

Yi-Chen Lu ◽

Sung Kyu Lim ◽

Krishnendu Chakrabarty

Keyword(s):

Power Supply ◽

Test Pattern ◽

Power Supply Noise ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

3D Ics ◽

Scan Test ◽

Supply Noise

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Transition delay fault testing of 3D ICs with IR-drop study

2012 IEEE 30th VLSI Test Symposium (VTS) ◽

10.1109/vts.2012.6231065 ◽

2012 ◽

Cited By ~ 4

Author(s):

Shreepad Panth ◽

Sung Kyu Lim

Keyword(s):

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Ir Drop ◽

3D Ics ◽

Transition Delay

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New advances in path delay fault testing of combinational circuits

Proceedings of IEEE VLSI Test Symposium ◽

10.1109/vtest.1994.292301 ◽

2002 ◽

Cited By ~ 3

Author(s):

X. Xie ◽

A. Albicki

Keyword(s):

Path Delay ◽

Combinational Circuits ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Path Delay Fault Testing

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Satisfiability-Based Functional Delay Fault Testing

VLSI: Systems on a Chip - IFIP Advances in Information and Communication Technology ◽

10.1007/978-0-387-35498-9_32 ◽

2000 ◽

pp. 362-372

Author(s):

Joonyoung Kim ◽

João Marques Silva ◽

Karem A. Sakallah

Keyword(s):

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Functional Delay

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A Novel Delay Fault Testing Methodology for Resistive Faults in Deep Sub-micron Technologies

Communications in Computer and Information Science - Advances in Computer Science and Engineering ◽

10.1007/978-3-540-89985-3_80 ◽

2008 ◽

pp. 653-660

Author(s):

Reza Javaheri ◽

Reza Sedaghat

Keyword(s):

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Testing Methodology

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A DFT technique for low frequency delay fault testing in high performance digital circuits

Proceedings. International Test Conference ◽

10.1109/test.2002.1041870 ◽

2003 ◽

Cited By ~ 4

Author(s):

B. Chatterjee ◽

M. Sachdev ◽

A. Keshavarzi

Keyword(s):

High Performance ◽

Digital Circuits ◽

Low Frequency ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing

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Path delay fault testing using test points

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/606603.606604 ◽

2003 ◽

Vol 8 (1) ◽

pp. 1-10 ◽

Cited By ~ 2

Author(s):

S. Tragoudas ◽

N. Denny

Keyword(s):

Path Delay ◽

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Path Delay Fault ◽

Test Points ◽

Path Delay Fault Testing

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A zero aliasing built-in self test technique for delay fault testing

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) ◽

10.1109/dftvs.1999.802874 ◽

2003 ◽

Cited By ~ 3

Author(s):

Y. Tsiatouhas ◽

T. Haniotakis

Keyword(s):

Fault Testing ◽

Test Technique ◽

Delay Fault ◽

Delay Fault Testing ◽

Self Test ◽

Built In Self Test

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Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing

13th Asian Test Symposium ◽

10.1109/ats.2004.47 ◽

2005 ◽

Author(s):

Ho Fai Ko ◽

N. Nicolici

Keyword(s):

Fault Testing ◽

Delay Fault ◽

Delay Fault Testing ◽

Scan Chain ◽

Scan Chain Design

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