Surface cleaning of silicon wafer by laser sparking

2001 ◽  
Vol 13 (4) ◽  
pp. 154-158 ◽  
Author(s):  
J. M. Lee ◽  
K. G. Watkins ◽  
W. M. Steen
Keyword(s):  
Silicon Wafer ◽  
Surface Cleaning

Effect of Surface Cleaning on Laser Texturing of Multicrystalline Silicon Wafer

2018 ◽  
Vol 10 (5) ◽  
pp. 690-693
Author(s):  
Hee Soo Kim ◽  
Seung Hyun Ha ◽  
Sang Joon Park ◽  
Ji Hyeon Kim
Keyword(s):  
Silicon Wafer ◽  
Surface Cleaning ◽  
Multicrystalline Silicon ◽  
Laser Texturing ◽  
Effect Of Surface

Study on the effect of Silicon surface cleaning processes on Gate Oxide Integrity

1997 ◽  
Vol 477 ◽  
Author(s):  
A. Corradi ◽  
E. Borzoni ◽  
P. Godio ◽  
G. Borionetti
Keyword(s):  
Experimental Design ◽  
Silicon Wafer ◽  
Silicon Surface ◽  
Surface Preparation ◽  
Gate Oxide ◽  
Surface Cleaning ◽  
Wafer Surface ◽  
Quality Performance ◽  
Wafer Cleaning ◽  
Silicon Wafer Surface

ABSTRACTThe effect of different silicon wafer surface preparation in modulating gate oxide quality performance has been studied through an experimental design which examines key phases of wafer cleaning and polishing processes. An interpretation of the root causes of GOI degradation has been proposed and discussed.

TEM characterization of silicon epitaxial layer grown on Si-TaS2, eutectic composites

1991 ◽  
Vol 49 ◽  
pp. 802-803
Author(s):  
C.M. Sung ◽  
M. Levinson ◽  
M. Tabasky ◽  
K. Ostreicher ◽  
B.M. Ditchek
Keyword(s):  
Substrate Surface ◽  
Bulk Sample ◽  
Surface Cleaning ◽  
Native Oxide ◽  
Czochralski Growth ◽  
Ion Milling ◽  
Cross Sectional ◽  
Cleaning Methods ◽  
Field Emission Cathodes

Directionally solidified Si/TaSi2 eutectic composites for the development of electronic devices (e.g. photodiodes and field-emission cathodes) were made using a Czochralski growth technique. High quality epitaxial growth of silicon on the eutectic composite substrates requires a clean silicon substrate surface prior to the growth process. Hence a preepitaxial surface cleaning step is highly desirable. The purpose of this paper is to investigate the effect of surface cleaning methods on the epilayer/substrate interface and the characterization of silicon epilayers grown on Si/TaSi2 substrates by TEM.Wafers were cut normal to the <111> growth axis of the silicon matrix from an approximately 1 cm diameter Si/TaSi2 composite boule. Four pre-treatments were employed to remove native oxide and other contaminants: 1) No treatment, 2) HF only; 3) HC1 only; and 4) both HF and HCl. The cross-sectional specimens for TEM study were prepared by cutting the bulk sample into sheets perpendicular to the TaSi2 fiber axes. The material was then prepared in the usual manner to produce samples having a thickness of 10μm. The final step was ion milling in Ar+ until breakthrough occurred. The TEM samples were then analyzed at 120 keV using the Philips EM400T.

Development of Silicon Wafer Packaging Technology for Deep UV LED

2020 ◽  
Vol 140 (7) ◽  
pp. 152-157
Author(s):  
Hirofumi Chiba ◽  
Yukio Suzuki ◽  
Yoshiaki Yasuda ◽  
Mitsuyasu Kumagai ◽  
Takaaki Koyama ◽  
...  
Keyword(s):  
Silicon Wafer ◽  
Packaging Technology ◽  
Uv Led ◽  
Deep Uv
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