scholarly journals Analytic models of CMOS logic in various regimes

2014 ◽  
Vol 11 (2) ◽  
pp. 269-290 ◽  
Author(s):  
Branko Dokic ◽  
Tatjana Pesic-Brdjanin ◽  
Rados Dabic
Keyword(s):  
Threshold Voltage ◽  
Digital Circuits ◽  
Constant Current ◽  
Functional Dependencies ◽  
Weak Inversion ◽  
Static And Dynamic Characteristics ◽  
Mos Transistor ◽  
Current Voltage ◽  
Analytic Models ◽  
First Time

In this paper, comparative analytic models of static and dynamic characteristics of CMOS digital circuits in strong, weak and mixed inversion regime have been described. Term mixed inversion is defined for the first time. The paper shows that there is an analogy in behavior and functional dependencies of parameters in all three CMOS regimes. Comparative characteristics of power consumption and speed in static regimes are given. Dependency of threshold voltage and logic delay time on temperature has been analyzed. Dynamic model with constant current is proposed. It is shown that digital circuits with dynamic threshold voltage of MOS transistor (DT-CMOS) have better logic delay characteristics. The analysis is based on simplified current-voltage MOS transistor models in strong and weak inversion regimes, as well as PSPICE software using 180 nm technology parameters.

scholarly journals Starter for Voltage Boost Converter to Harvest Thermoelectric Energy for Body-Worn Sensors

Energies ◽  
2021 ◽  
Vol 14 (14) ◽  
pp. 4092
Author(s):  
Grzegorz Blakiewicz ◽  
Jacek Jakusz ◽  
Waldemar Jendernalik
Keyword(s):  
Threshold Voltage ◽  
Low Voltage ◽  
Boost Converter ◽  
Mos Transistors ◽  
Weak Inversion ◽  
Thermoelectric Energy ◽  
On Chip ◽  
Voltage Swing ◽  
High Output Voltage ◽  
High Output

This paper examines the suitability of selected configurations of ultra-low voltage (ULV) oscillators as starters for a voltage boost converter to harvest energy from a thermoelectric generator (TEG). Important properties of particularly promising configurations, suitable for on-chip implementation are compared. On this basis, an improved oscillator with a low startup voltage and a high output voltage swing is proposed. The applicability of n-channel native MOS transistors with negative or near-zero threshold voltage in ULV oscillators is analyzed. The results demonstrate that a near-zero threshold voltage transistor operating in the weak inversion region is most advantageous for the considered application. The obtained results were used as a reference for design of a boost converter starter intended for integration in 180-nm CMOS X-FAB technology. In the selected technology, the most suitable transistor available with a negative threshold voltage was used. Despite using a transistor with a negative threshold voltage, a low startup voltage of 29 mV, a power consumption of 70 µW, and power conversion efficiency of about 1.5% were achieved. A great advantage of the proposed starter is that it eliminates a multistage charge pump necessary to obtain a voltage of sufficient value to supply the boost converter control circuit.

Rapid Thermal Oxidation of Lightly Doped Silicon in N2O

1994 ◽  
Vol 342 ◽  
Author(s):  
S.C. Sun ◽  
L.S. Wang ◽  
F.L. Yeh ◽  
T.S. Lai ◽  
Y.H. Lin
Keyword(s):  
Growth Rate ◽  
Thermal Oxidation ◽  
Charge Trapping ◽  
Interface State ◽  
Constant Current ◽  
Mos Capacitor ◽  
Rapid Thermal Oxidation ◽  
Doped Silicon ◽  
State Generation ◽  
First Time

ABSTRACTIn this paper, a detailed study is presented for the growth kinetics of rapid thermal oxidation of lightly-doped silicon in N2O and O2 on (100), (110), and (111) oriented substrates. It was found that (110)-oriented Si has the highest growth rate in both N2O and dry O2, and (100) Si has the lowest rate. There is no “crossover” on the growth rate of rapid thermal N2O oxidation between (110) Si and (111) Si as compared to oxides grown in furnace N2O. Pressure dependence of rapid thermal N2O oxidation is reported for the first time. MOS capacitor results show that the low-pressure (40 Torr) N2O-grown oxides have much less interface state generation and charge trapping under constant current stress as compared to oxides grown in either 760 Torr N2O or O2 ambient.

scholarly journals Self-Cascode Current-Voltage Curve-Construction Algorithm from Single MOSFET Measurements for Analog Figures-of-Merit Extraction

2019 ◽  
Vol 14 (1) ◽  
pp. 1-6
Author(s):  
Li�gia Martins d'Oliveira ◽  
Valeriya Kilchytska ◽  
Denis Flandre ◽  
Michelly De Souza
Keyword(s):  
Threshold Voltage ◽  
Extraction Method ◽  
New Technologies ◽  
Experimental Measurements ◽  
Saturation Regime ◽  
Figures Of Merit ◽  
Voltage Curve ◽  
Current Voltage ◽  
Current Voltage Curve ◽  
Self Cascode

This paper proposes a curve extraction method for I-V curves and analog figures-of-merit of self-cascode MOSFET associations (SC) using a code that exploits I-V curves of single transistors as input. The method was validated by using experimental measurements of fabricated SC and the very single transistors that compose them. The results indicate a very low error between the SC generated by the code and the measured reference for operation in saturation regime and above threshold voltage, for both the I-V curves and their derivatives. This method is then valid for the assessment of the SC structures in new technologies, avoiding experimental dedicated layouts or complex set-ups.

Evaluation of SiC Stack Cascode for 200°C Operations

2014 ◽  
Vol 778-780 ◽  
pp. 879-882 ◽  
Author(s):  
Xue Qing Li ◽  
Petre Alexandrov ◽  
John Hostetler ◽  
Anup Bhalla
Keyword(s):  
Dynamic Characteristics ◽  
Threshold Voltage ◽  
Load Condition ◽  
Experimental Results ◽  
Reliability Test ◽  
Inductive Load ◽  
Static And Dynamic Characteristics

This paper evaluates the static and dynamic characteristics of a 1.2kV SiC stack-cascode at junction temperatures (Tj) up to 200°C. The experimental results show that, at Tj = 200°C, the SiC stack-cascode can be switched stably under a 600V-17A inductive load condition and can withstand an avalanche current of 13A for 9μs (Eav = 116mJ) for a 1.5mH load inductor. The SiC stack-cascode has no degradation in on-resistance, threshold voltage and blocking characteristics after 80 hours HTRB reliability test at 200°C ambient. These promising experimental results indicate the possibility of the SiC stack-cascode for reliable 200°C operations.

scholarly journals Reevaluation of Performance of Electric Double-layer Capacitors from Constant-current Charge/Discharge and Cyclic Voltammetry

2016 ◽  
Vol 6 (1) ◽  
Author(s):  
Anis Allagui ◽  
Todd J. Freeborn ◽  
Ahmed S. Elwakil ◽  
Brent J. Maundy
Keyword(s):  
Cyclic Voltammetry ◽  
Double Layer ◽  
Time Domain ◽  
Electric Double Layer ◽  
Constant Current ◽  
Step Response ◽  
Current Voltage ◽  
The Time Domain ◽  
Double Layer Capacitors ◽  
Electric Double Layer Capacitors

Abstract The electric characteristics of electric-double layer capacitors (EDLCs) are determined by their capacitance which is usually measured in the time domain from constant-current charging/discharging and cyclic voltammetry tests, and from the frequency domain using nonlinear least-squares fitting of spectral impedance. The time-voltage and current-voltage profiles from the first two techniques are commonly treated by assuming ideal S s C behavior in spite of the nonlinear response of the device, which in turn provides inaccurate values for its characteristic metrics. In this paper we revisit the calculation of capacitance, power and energy of EDLCs from the time domain constant-current step response and linear voltage waveform, under the assumption that the device behaves as an equivalent fractional-order circuit consisting of a resistance R s in series with a constant phase element (CPE(Q, α), with Q being a pseudocapacitance and α a dispersion coefficient). In particular, we show with the derived (R s , Q, α)-based expressions, that the corresponding nonlinear effects in voltage-time and current-voltage can be encompassed through nonlinear terms function of the coefficient α, which is not possible with the classical R s C model. We validate our formulae with the experimental measurements of different EDLCs.

scholarly journals An Improved Analysis for the Harmonic Distortion of MOS Voltage-Controlled-Resistors

1997 ◽  
Vol 19 (4) ◽  
pp. 253-260
Author(s):  
Muhammad Taher Abuelma'atti
Keyword(s):  
Fourth Order ◽  
Harmonic Distortion ◽  
Voltage Characteristic ◽  
Current Voltage Characteristic ◽  
Mos Transistor ◽  
Current Voltage ◽  
Order Polynomial ◽  
Polynomial Expression ◽  
Analytical Expressions ◽  
Fourth Order Polynomial

In this paper, a fourth-order polynomial expression is obtained for the nonlinear current-voltage characteristic of a MOS transistor operating in the triode region. Using this expression, closed-form expressions are obtained for the second-, third- and fourth-harmonic distortion of a MOS voltage-controlled- resistors. The analytical expressions obtained in this paper can be used for a quantitative study of the effect of different parameters of the performance of MOS voltage-controlled-resistors.

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