scholarly journals Parallel execution tracing: An alternative solution to exploit under-utilized resources in multi-core architectures for control-flow checking

2016 ◽  
Vol 29 (2) ◽  
pp. 243-260 ◽  
Author(s):  
Mohammad Maghsoudloo ◽  
Hamid Zarandi
Keyword(s):  
Parallel Execution ◽  
Control Flow ◽  
Experimental Results ◽  
Alternative Solution ◽  
Simulation Environment ◽  
Detection Coverage ◽  
Control Flow Checking ◽  
And Performance ◽  
Execution Tracing ◽  
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In this paper, a software behavior-based technique is presented to detect control-flow errors in multi-core architectures. The analysis of a key point leads to introduction of the proposed technique: employing under-utilized CPU resources in multi-core processors to check the execution flow of the programs concurrently and in parallel with the main executions. To evaluate the proposed technique, a quad-core processor system was used as the simulation environment, and the behavior of SPEC CPU2006 benchmarks were studied as the target to compare with conventional techniques. The experimental results, with regard to both detection coverage and performance overhead, demonstrate that on average, about 94% of the control-flow errors can be detected by the proposed technique, with less performance overhead compared to previous techniques. <br><br><font color="red"><b> This article has been retracted. Link to the retraction <u><a href="http://dx.doi.org/10.2298/FUEE1801155E">10.2298/FUEE1801155E</a><u></b></font>

scholarly journals Retraction: Mohammad Maghsoudloo, Hamid R. Zarandi: Parallel execution tracing: An alternative solution to exploit under-utilized resources in multi-core architectures for control-flow checking. Facta universitatis, series: Electronics and Energetics (FU Elec Energ), vol. 29, no 2, june 2016, pp. 243-260. DOI: 10.2298/FUEE1602243M

2018 ◽  
Vol 31 (1) ◽  
pp. 155-155
Author(s):  
E Editorial
Keyword(s):  
Parallel Execution ◽  
Control Flow ◽  
Alternative Solution ◽  
Adaptive Software ◽  
Retracted Article ◽  
Microelectronics Reliability ◽  
Control Flow Checking ◽  
Execution Tracing ◽  
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The article: PARALLEL EXECUTION TRACING: AN ALTERNATIVE SOLUTION TO EXPLOIT UNDER-UTILIZED RESOURCES IN MULTI-CORE ARCHITECTURES FOR CONTROL-FLOW CHECKING. Mohammad Maghsoudloo, Hamid R. Zarandi. Facta Universitatis, Series: Electronics and Energetics, Vol. 29, No 2, June 2016, pp. 243-260, DOI: 10.2298/FUEE1602243M, repeats 62% data already published in: An efficient adaptive software-implemented technique to detect control-flow errors in multi-core architectures. Mohammad Maghsoudloo, Hamid R. Zarandi, Navid Khoshavi. Microelectronics Reliability, Vol. 52, Issue 11, November 2012, pp. 2812-2828, DOI: doi.org/10.1016/j.microrel.2012.03.033 without any referencing. <br><br><font color="red"><b> Link to the retracted article <u><a href="http://dx.doi.org/10.2298/FUEE1602243M ">10.2298/FUEE1602243M </a></b></u>

Platform Independent Analysis of Probabilities on Multithreaded Programs

2013 ◽  
Vol 1 (3) ◽  
pp. 48-65
Author(s):  
Yuting Chen
Keyword(s):  
Operating System ◽  
Static Analysis ◽  
Main Idea ◽  
Experimental Results ◽  
Machine To Machine ◽  
Concurrent Program ◽  
Acceptable Accuracy ◽  
Multithreaded Programs ◽  
Independent Analysis ◽  
And Performance

A concurrent program is intuitively associated with probability: the executions of the program can produce nondeterministic execution program paths due to the interleavings of threads, whereas some paths can always be executed more frequently than the others. An exploration of the probabilities on the execution paths is expected to provide engineers or compilers with support in helping, either at coding phase or at compile time, to optimize some hottest paths. However, it is not easy to take a static analysis of the probabilities on a concurrent program in that the scheduling of threads of a concurrent program usually depends on the operating system and hardware (e.g., processor) on which the program is executed, which may be vary from machine to machine. In this paper the authors propose a platform independent approach, called ProbPP, to analyzing probabilities on the execution paths of the multithreaded programs. The main idea of ProbPP is to calculate the probabilities on the basis of two kinds of probabilities: Primitive Dependent Probabilities (PDPs) representing the control dependent probabilities among the program statements and Thread Execution Probabilities (TEPs) representing the probabilities of threads being scheduled to execute. The authors have also conducted two preliminary experiments to evaluate the effectiveness and performance of ProbPP, and the experimental results show that ProbPP can provide engineers with acceptable accuracy.

scholarly journals Microcontroller Based Flexible Modulation Scheme of MLI Operation for Selective Lower Levels: A Knowledge Based Approach

2016 ◽  
Vol 2016 ◽  
pp. 1-11
Author(s):  
R. K. Dhatrak ◽  
R. K. Nema ◽  
D. M. Deshpande
Keyword(s):  
Pulse Generation ◽  
Multilevel Inverter ◽  
Experimental Results ◽  
Modulation Scheme ◽  
Inductive Load ◽  
Medium Voltage ◽  
Knowledge Based ◽  
Common Mode Voltage ◽  
Power Modules ◽  
And Performance

In today’s industrial world multilevel inverter (MLI) got a significant importance in medium voltage application and also a very potential topic for researchers. It is experienced that studying and comparing results of multilevel inverter (MLI) at distinct levels are a costlier and time consuming issue for any researcher if he fabricate different inverters for each level, as designing power modules simultaneously for different level is a cumbersome task. In this paper a flexible quotient has been proposed to recognize possible conversion of available MLI to few lower level inverters by appropriately changing microcontroller programming. This is an attempt to obtain such change in levels through simulation using MATLAB Simulink on inductive load which may also be applied to induction motor. Experimental results of pulse generation using dsPIC33EP256MC202 demonstrate the feasibility of proposed scheme. Proposed flexible quotient successfully demonstrates that a five-level inverter may be operated as three and two levels also. The paper focuses on odd levels only as common mode voltage (CMV) can be reduced to zero and performance of drives is better than even level. Simulated and experimental results are given in paper.

AN EFFECTIVE CONTROL FLOW CHECKING METHOD FOR MULTITASK PROCESSING IN HARSH ENVIRONMENTS

2013 ◽  
Vol 22 (08) ◽  
pp. 1350067 ◽  
Author(s):  
SEYYED AMIR ASGHARI ◽  
ATENA ABDI ◽  
OKYAY KAYNAK ◽  
HASSAN TAHERI ◽  
HOSSEIN PEDRAM
Keyword(s):  
Error Detection ◽  
Optimal Solution ◽  
Control Flow ◽  
Simultaneous Optimization ◽  
Harsh Environments ◽  
Effective Control ◽  
Power Performance ◽  
Single Event Upsets ◽  
Novel Method ◽  
And Performance

Electronic equipment used in harsh environments such as space has to cope with many threats. One major threat is the intensive radiation which gives rise to Single Event Upsets (SEU) that lead to control flow errors and data errors. In the design of embedded systems to be used in space, the use of radiation tolerant equipment may therefore be a necessity. However, even if the higher cost of such a choice is not a problem, the efficiency of such equipment is lower than the COTS equipment. Therefore, the use of COTS with appropriate measures to handle the threats may be the optimal solution, in which a simultaneous optimization is carried out for power, performance, reliability and cost. In this paper, a novel method is presented for control flow error detection in multitask environments with less memory and performance overheads as compared to other methods seen in the literature.

scholarly journals Investigation of Data Dependencies by Dynamic Analysis of Sapfor

2020 ◽  
Vol 23 (3) ◽  
pp. 473-493
Author(s):  
Nikita Andreevich Kataev ◽  
Alexander Andreevich Smirnov ◽  
Andrey Dmitrievich Zhukov
Keyword(s):  
Dynamic Analysis ◽  
Programming Languages ◽  
Static Analysis ◽  
Automatic Parallelization ◽  
Parallel Execution ◽  
Control Flow ◽  
Analysis Tool ◽  
Data Dependencies ◽  
Program Parallelization ◽  
Memory Accesses

The use of pointers and indirect memory accesses in the program, as well as the complex control flow are some of the main weaknesses of the static analysis of programs. The program properties investigated by this analysis are too conservative to accurately describe program behavior and hence they prevent parallel execution of the program. The application of dynamic analysis allows us to expand the capabilities of semi-automatic parallelization. In the SAPFOR system (System FOR Automated Parallelization), a dynamic analysis tool has been implemented, based on on the instrumentation of the LLVM representation of an analyzed program, which allows the system to explore programs in both C and Fortran programming languages. The capabilities of the static analysis implemented in SAPFOR are used to reduce the overhead program execution, while maintaining the completeness of the analysis. The use of static analysis allows to reduce the number of analyzed memory accesses and to ignore scalar variables, which can be explored in a static way. The developed tool was tested on performance tests from the NAS Parallel Benchmarks package for C and Fortran languages. The implementation of dynamic analysis, in addition to traditional types of data dependencies (flow, anit, output), allows us to determine privitizable variables and a possibility of pipeline execution of loops. Together with the capabilities of DVM and OpenMP these greatly facilitates program parallelization and simplify insertion of the appropriate compiler directives.

scholarly journals Reconciling optimization with secure compilation

2021 ◽  
Vol 5 (OOPSLA) ◽  
pp. 1-30
Author(s):  
Son Tuan Vu ◽  
Albert Cohen ◽  
Arnaud De Grandmaison ◽  
Christophe Guillon ◽  
Karine Heydemann
Keyword(s):  
Side Effects ◽  
Control Flow ◽  
Partial Ordering ◽  
Input Output ◽  
Machine Code ◽  
Fine Grained ◽  
Control Flow Integrity ◽  
Correct Execution ◽  
Source Level ◽  
And Performance

Software protections against side-channel and physical attacks are essential to the development of secure applications. Such protections are meaningful at machine code or micro-architectural level, but they typically do not carry observable semantics at source level. This renders them susceptible to miscompilation, and security engineers embed input/output side-effects to prevent optimizing compilers from altering them. Yet these side-effects are error-prone and compiler-dependent. The current practice involves analyzing the generated machine code to make sure security or privacy properties are still enforced. These side-effects may also be too expensive in fine-grained protections such as control-flow integrity. We introduce observations of the program state that are intrinsic to the correct execution of security protections, along with means to specify and preserve observations across the compilation flow. Such observations complement the input/output semantics-preservation contract of compilers. We introduce an opacification mechanism to preserve and enforce a partial ordering of observations. This approach is compatible with a production compiler and does not incur any modification to its optimization passes. We validate the effectiveness and performance of our approach on a range of benchmarks, expressing the secure compilation of these applications in terms of observations to be made at specific program points.

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