CFCET: A hardware-based control flow checking technique in COTS processors using execution tracing

2006 ◽  
Vol 46 (5-6) ◽  
pp. 959-972 ◽  
Author(s):  
Amir Rajabzadeh ◽  
Seyed Ghassem Miremadi
Keyword(s):  
Control Flow ◽  
Control Flow Checking ◽  
Execution Tracing

scholarly journals Parallel execution tracing: An alternative solution to exploit under-utilized resources in multi-core architectures for control-flow checking

2016 ◽  
Vol 29 (2) ◽  
pp. 243-260 ◽  
Author(s):  
Mohammad Maghsoudloo ◽  
Hamid Zarandi
Keyword(s):  
Parallel Execution ◽  
Control Flow ◽  
Experimental Results ◽  
Alternative Solution ◽  
Simulation Environment ◽  
Detection Coverage ◽  
Control Flow Checking ◽  
And Performance ◽  
Execution Tracing ◽  
Font Color

In this paper, a software behavior-based technique is presented to detect control-flow errors in multi-core architectures. The analysis of a key point leads to introduction of the proposed technique: employing under-utilized CPU resources in multi-core processors to check the execution flow of the programs concurrently and in parallel with the main executions. To evaluate the proposed technique, a quad-core processor system was used as the simulation environment, and the behavior of SPEC CPU2006 benchmarks were studied as the target to compare with conventional techniques. The experimental results, with regard to both detection coverage and performance overhead, demonstrate that on average, about 94% of the control-flow errors can be detected by the proposed technique, with less performance overhead compared to previous techniques. <br><br><font color="red"><b> This article has been retracted. Link to the retraction <u><a href="http://dx.doi.org/10.2298/FUEE1801155E">10.2298/FUEE1801155E</a><u></b></font>

scholarly journals Retraction: Mohammad Maghsoudloo, Hamid R. Zarandi: Parallel execution tracing: An alternative solution to exploit under-utilized resources in multi-core architectures for control-flow checking. Facta universitatis, series: Electronics and Energetics (FU Elec Energ), vol. 29, no 2, june 2016, pp. 243-260. DOI: 10.2298/FUEE1602243M

2018 ◽  
Vol 31 (1) ◽  
pp. 155-155
Author(s):  
E Editorial
Keyword(s):  
Parallel Execution ◽  
Control Flow ◽  
Alternative Solution ◽  
Adaptive Software ◽  
Retracted Article ◽  
Microelectronics Reliability ◽  
Control Flow Checking ◽  
Execution Tracing ◽  
Font Color

The article: PARALLEL EXECUTION TRACING: AN ALTERNATIVE SOLUTION TO EXPLOIT UNDER-UTILIZED RESOURCES IN MULTI-CORE ARCHITECTURES FOR CONTROL-FLOW CHECKING. Mohammad Maghsoudloo, Hamid R. Zarandi. Facta Universitatis, Series: Electronics and Energetics, Vol. 29, No 2, June 2016, pp. 243-260, DOI: 10.2298/FUEE1602243M, repeats 62% data already published in: An efficient adaptive software-implemented technique to detect control-flow errors in multi-core architectures. Mohammad Maghsoudloo, Hamid R. Zarandi, Navid Khoshavi. Microelectronics Reliability, Vol. 52, Issue 11, November 2012, pp. 2812-2828, DOI: doi.org/10.1016/j.microrel.2012.03.033 without any referencing. <br><br><font color="red"><b> Link to the retracted article <u><a href="http://dx.doi.org/10.2298/FUEE1602243M ">10.2298/FUEE1602243M </a></b></u>

Software Based Methods to Harden Embedded Software at Run-Time: A Survey

2015 ◽  
Author(s):  
Michael Kramer ◽  
Martin Horauer
Keyword(s):  
Embedded Systems ◽  
Computer Systems ◽  
Computer Software ◽  
Control Flow ◽  
Test Procedures ◽  
Modern Computer ◽  
Systems Software ◽  
Personal Computer Software ◽  
Control Flow Checking ◽  
Run Time

Embedded Systems software reliability is increasingly important, therefore methods to harden existing software are needed. In general, hardening software against various failures is a necessity in modern computer systems. A lot of work has been published regarding many possible ways to achieve this non-functional requirement. Relevant topics include, e.g., test procedures, recommended development flows, and hardware measures like watchdog timers. One of these methods seems very promising to be software implemented in modern embedded systems: Control Flow Checking by signatures. Various authors have shown the effectiveness and feasibility of Control Flow Checking (CFC) by signatures for personal computer software. For instance it has been shown for standard computer-systems, that CFC is capable of reducing undetected control flow errors by at least one magnitude. This survey will focus on the applicability of such software hardening methods to embedded systems, while adhering mainly to software based approaches. Published methods will be summarized and compared. Furthermore methods to simplify derived control-flow graphs to essential states will be emphasized. Finally the possibility to apply run-time verification to the Control-flow Checking Software is considered.

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